Since the FPGA's memory on the Arty S7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This configuration mode is called Master
SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To that effect, a configuration file needs to be downloaded first
to the flash. When programming a non-volatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can
program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). This is called indirect
programming. After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper
setting (see Figure 2.1). Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written however, FPGA
configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration
speed. The Arty S7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz () for Quad-SPI programming.
Quad-SPI programming can be done using the hardware manager in Vivado.
The Arty S7 includes one MT41K128M16JT-125 memory component, creating a single rank, 16-bit wide interface. It is routed to a 1.35V-powered HR (High Range) FPGA bank with
50 ohm controlled single-ended trace impedance. 50 ohm internal terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side, on-die
terminations (ODT) are used for impedance matching.
For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The easiest way to accomplish this on the Arty
S7 is to use the Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard. The MIG Wizard can generate a native FIFO-style or an
AXI4 interface to connect to user logic. This workflow allows the customization of several DDR parameters optimized for the particular application. Table 3.1 below lists the MIG
Wizard settings optimized for the Arty S7 (any settings not mentioned can be left in default state).
Setting
Value
Memory type
DDR3 SDRAM
Max. clock period
3077ps (650Mbps data rate)
Memory part
MT41K128M16XX-15E
Memory Voltage
1.35V
Data width
16
Data mask
Enabled
Recommended Input Clock Period
10000ps (100.000 MHz ())
Output Driver Impedance Control
RZQ/6
Controller Chip Select pin
Enabled
Rtt (nominal) – On-die termination
RZQ/6
Internal Vref
Enabled
Internal termination impedance
50ohms
Table 3.1. DDR3L settings for the Arty S7.
For clocking, it is recommending that the System clock be set to “Single-ended”, and connected directly to the onboard 100MHz oscillator on pin R2. The Reference clock should be
set to “no buffer” and can be connected to a 200 MHz () clock generated from a clocking wizard elsewhere in the design. It is also possible to generate the reference clock from the
MIG itself by enabling “Select Additional Clocks” and generating a clock with a 5007 ps period (199.69231 MHz ()). This clock will be within spec () for the reference clock
requirements, and can be looped around back into the reference clock input of the MIG IP core.
The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is
provided on the Arty S7 resource center to speed up this process. It is included in the digilent-mig repository on the
Digilent Github
(https://github.com/Digilent)
. This download
also includes a .prj file that can be imported into the wizard to automatically configure it with the options found in Table 3.1.
For those using the MIG with a MicroBlaze project, it is not necessary to use the files found in the digilent-mig repository. Instead, the Arty S7 MIG settings and pinout will be
automatically imported from the
Digilent Vivado board files
(https://reference.digilentinc.com/reference/software/vivado/board-files)
.
For more details on the Xilinx MIG, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586).
FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S), and setting the mode jumper will cause the FPGA to automatically read a
configuration from this device at power on. A Spartan-7 50T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~13.92 MB ()) available
for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded
and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into your bitstream, and then program
the bitstream and large microblaze program into the Quad SPI Flash using Xilinx SDK.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI
Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Spansion's datasheet for the
flash device to learn how to implement a custom controller.
All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O, except for SCK. It can only be accessed by
instantiating a special primitive called STARTUPE2. The Xilinx AXI Quad SPI IP core has a configuration option that will automatically instantiate the primitive for you, and this
option should be enabled when using it with the Arty S7. For information on instantiating the primitive from HDL, refer to the “Vivado Design Suite 7 Series FPGA and Zynq-7000
All Programmable SoC Libraries Guide” (UG953) from Xilinx.
2.2 Quad-SPI Configuration
3 DDR3L Memory
4 Quad-SPI Flash
