Digi Errata NS9750B-A1 Скачать руководство пользователя страница 4

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N S 9 7 5 0 B - A 1   E r r a t a ,   R e v .   F     0 9 / 2 0 0 6

U S B   O V R   a n d   U S B   P W R

„

The maximum bytes in each DMA buffer descriptor is limited to 16 bytes.

„

The maximum skid rate can be up to 16 characters.

„

The serial monitor thread is changed to handle the missing CTS interrupt.

See the appropriate (6.0 or 6.3) NET+OS SW toolkit (on the Web) for the required software 
workarounds.

Hardware workaround: For each UART, externally clock the CTS signal with the Txd_n signal to 
guarantee that CTS will not be seen de-asserting at the start of a character.

USB OVR and USB PWR

The USB OVR (over current) input on gpio[16] is not shown in the GPIO MUX pinout tables. The 
polarity of this signal cannot be changed. It is true high, normally requiring an external inverter 
and noise filter to prevent false indications of over current.

This table shows the corrections to GPIO[16] in the pinout table:

Updates are required to the BSP to change gpio[16] from mode 00 to mode 02. Timer 11 is 
disabled, allowing USB OVR to be recognized by the USP IP. Even though Timer 11 is disabled, the 
Timer clock select field must be set to 111-External pulse event to set GPIO[16] to an input.

If you are using USB Host, GPIO[16] must be reserved for the USB OVR function.

CTS[n]

74LV74

D

Q

CLK

Q

PR

CL

TXD[n]

UART CTS Flow
Control workaround

R2

0 OHM

CTS[n]

U2

RESET

TXD[n]

Add R2 instead of U2 to bypass this circuit

CTS_mod[n]

Signal

Mode

Description

00

01

02

03 (default)

Reserved output

 1284 nFault (peripheral driver, duplicate)

Timer 11 (duplicate), USB OVR

 GPIO 16

gpio[16]

Содержание Errata NS9750B-A1

Страница 1: ...ch 2006 Technical Support Phone 1 877 912 3444 Web techpubs digi com SPI slave data output high impedance control UART gap timer UART CTS related transmit data errors USB OVR and USB PWR PCI arbiter s...

Страница 2: ...rruption occur when a start bit is missed Software workaround Three conditions have been identified for this erratum Applications with a steady stream of receive data are not affected if the buffer ga...

Страница 3: ...pin on each UART This function is controlled by the RXEXT bit 27 in each Serial Bit rate register If multiple UARTs are running at the same baud rate one baud clock can be used for the multiple UARTs...

Страница 4: ...of this signal cannot be changed It is true high normally requiring an external inverter and noise filter to prevent false indications of over current This table shows the corrections to GPIO 16 in t...

Страница 5: ...data FIFO overflow Ethernet receiver stall The Ethernet receiver intermittently locks up in 100 Mbps half duplex applications due to an overflow in the RX data FIFO Workaround Reset the RX Ethernet lo...

Страница 6: ...TXBD RAM Workaround Software keeps a shadow copy of the TXBD RAM flags in main memory and updates the copy only when the CPU accesses the TXBD RAM When the CPU receives an Ethernet TX ERROR interrupt...

Страница 7: ......

Страница 8: ...and other countries worldwide All other trademarks are the property of their respective owners Information in this manual is subject to change without notice and does not represent a commitment on th...

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