
ConnectCore
f or
i.MX51
©
2011
Digi
International,
Inc.
12
Block Diagram
The next figures show the block diagram of the Freescale i.MX515 CPU and the block diagram
of the ConnectCore for i.MX51 module.
CPU
Security
SAHARA v4
OpenGL ES 2 0 + VG1 1
Mory
ROM 32KB
SAHARA v4
Trust Zone
RTIC
SCC v2
OpenGL ES 2.0 + VG1.1
HW Video Codecs
HD720 TV-Out
ROM 32KB
RAM 96KB
rs
Ti
3
ARM C
SRTC
Syste Control
Secure JTAG
Timer x 3
PWM x 2
ARMCore
600/800 Cortex-A8
32KB
I-Cache
32KB
D-Cache
256KB
L2-Cache
Power Mgmt
PLL x 3
Clock Reset
Neon
Vector Floag Point Unit
ETM
External Memory
Interface
Processin Unit
Fast IrDA
1-Wire
I
2
C x 2
HS MMC /SDIO x 4
Smart DMA
/AHBSwitch Fric
Dual-Display Controller
Image Signal Processor
Resizing & Blending
Inversion & Rotaon
GPIO
Keypad
USB OTG Host + PHY
SSI/I2S x 3
UART x 3
CSPI HS x 2 / LS x 1
Inversion & Rotaon
Dual-Camera Interface
USB Host x 3
Fuse Box
SPDIF Tx
10/100 Ethernet x
WatchDog x 2
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