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Diamond Systems GPIO-MM, Руководство пользователя

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Diamond Systems Corporation                            GPIO-MM FPGA Pinout Guide V1.01 

Page 3 

1  GENERAL DESCRIPTION 

The FPGA on the GPIO-MM is connected to the following devices: 

 

1.1  PC/104 connectors J1 and J2 

The FPGA connects directly to the PC/104 signals:  

Address bus: SA<19:0>  

Data bus: SD<15:0> 

Control lines: AEN, IOR#, IOW#, SMEMRD#, SMEMWR#, MEMRD#, MEMWR#, TC, RESET 

16-bit control: IOCS16#, MEMCS16#, SBHE# 

 

IRQ and DMA signals are routed through configuration blocks J7-J9. 

 

1.2  External I/O connectors J3, J4, J5 and J6 

The FPGA I/O lines are connected directly to J3, J5 and J6.  DA108S1 chips provide ESD and overvoltage 
protection for these lines. 

The FPGA I/O lines are connected to J4 through 74XX245 buffers, described below. 

J6 is the JTAG port used to program the FPGA and the configuration PROM.   

 

1.3  Jumper configuration blocks J7, J8, J9 and J10 

J7 and J9 route IRQs as shown below: 

  

 

The IRQA and IRQB signals connect to the FPGA and can be routed through jumpers to the IRQx signals 
on the PC/104 bus.   

The  IRQPDA  and  IRQPDB  positions  allow  the  IRQ  signals  to  be  used  in  the  IRQ-sharing  configuration 
outlined by the PC/104 specification.  By installing a jumper on these positions, the corresponding IRQ line 
is  pulled  down  to  ground  through  a  1Kohm  resistor.    In  this  configuration,  the FPGA should either place 
the  IRQ  signal  in  input  mode  (to  indicate  an  idle  IRQ  status)  or  drive  the  line  to  the  high  logic  state  (to 
indicate active IRQ status). 

Содержание GPIO-MM

Страница 1: ...GPIO MM FPGA based PC 104 FPGA Pinout Guide V1 01 Copyright 2007 Diamond Systems Corporation 1255 Terra Bella Ave Mountain View CA 94043 Tel 650 810 2500 Fax 650 810 2525 www diamondsystems com ...

Страница 2: ...104 CONNECTORS J1 AND J2 3 1 2 EXTERNAL I O CONNECTORS J3 J4 J5 AND J6 3 1 3 JUMPER CONFIGURATION BLOCKS J7 J8 J9 AND J10 3 1 4 40MHZ OSCILLATOR Y1 5 1 5 STATUS LED D1 5 1 6 XCF02S CONFIGURATION PROM U9 5 1 7 256 BYTE 24C04 EEPROM U12 5 1 8 74XX164 SHIFT REGISTER U11 5 1 9 74XX245 BUFFERS U2 U7 5 2 PIN DEFINITIONS 6 ...

Страница 3: ... lines The FPGA I O lines are connected to J4 through 74XX245 buffers described below J6 is the JTAG port used to program the FPGA and the configuration PROM 1 3 Jumper configuration blocks J7 J8 J9 and J10 J7 and J9 route IRQs as shown below The IRQA and IRQB signals connect to the FPGA and can be routed through jumpers to the IRQx signals on the PC 104 bus The IRQPDA and IRQPDB positions allow t...

Страница 4: ... for the I O on J3 and is not related to the FPGA pinout J10 provides user defined configuration jumpers In the drawing above SP_PS1 CFG3 SP_PS0 CFG2 RS4XX CFG1 and RS232 CFG0 Each of the CFG 9 0 signals are connected to an FPGA input pin If the jumper is not present on J10 the signal will be pulled up to 3 3V If the jumper is present the signal is pulled low to 0V These inputs can be used for any...

Страница 5: ... The eight outputs lines of the 74XX164 each drive one LED on the lower left side of the board This is used in the standard logic to display the current personality ID but can be used for any purpose in a custom FPGA design It is connected to the FPGA through 2 wires 1 9 74XX245 buffers U2 U7 These buffers sit between J4 and the FPGA and provide higher I O current capability to J4 than the FPGA co...

Страница 6: ...18 Digital I O DIO_J3_19 E4 I O J3 pin 19 Digital I O DIO_J3_20 D1 I O J3 pin 20 Digital I O DIO_J3_21 D2 I O J3 pin 21 Digital I O DIO_J3_22 C1 I O J3 pin 22 Digital I O DIO_J3_23 C2 I O J3 pin 23 Digital I O DIO_J3_24 B1 I O J3 pin 24 Digital I O DIO_J3_25 A2 I O J3 pin 25 Digital I O DIO_J3_26 B3 I O J3 pin 26 Digital I O DIO_J3_27 A3 I O J3 pin 27 Digital I O DIO_J3_28 B4 I O J3 pin 28 Digital...

Страница 7: ...3 Digital I O DIO_J4_17 T9 I O J4 pin 17 U4 Digital I O DIO_J4_18 R7 I O J4 pin 18 U5 Digital I O DIO_J4_19 R9 I O J4 pin 19 U4 Digital I O DIO_J4_20 T7 I O J4 pin 20 U5 Digital I O DIO_J4_21 T10 I O J4 pin 21 U4 Digital I O DIO_J4_22 P7 I O J4 pin 22 U5 Digital I O DIO_J4_23 R10 I O J4 pin 23 U4 Digital I O DIO_J4_24 N7 I O J4 pin 24 U5 Digital I O DIO_J4_25 N9 I O J4 pin 25 U4 Digital I O DIO_J4...

Страница 8: ...104 Bus Clock PC 104 BUS AND CONFIGURATION GROUP IOW C13 In PC 104 B13 I O Write Strobe IOR B13 In PC 104 B14 I O Read Strobe IOCS16 A14 I O PC 104 D2 16 bit I O Access AEN H16 In PC 104 A11 Address Enable SMEMWR D12 In PC 104 B11 Memory Write 1MB SMEMRD C12 In PC 104 B12 Memory Read 1MB MEMWR B12 In PC 104 C10 Memory Write MEMRD A12 In PC 104 C9 Memory Read MEMCS16 A13 I O PC 104 D1 16 bit Memory...

Страница 9: ... A4 Data Bus SD4 K14 I O PC 104 A5 Data Bus SD3 K12 I O PC 104 A6 Data Bus SD2 J14 I O PC 104 A7 Data Bus SD1 J15 I O PC 104 A8 Data Bus SD0 J16 I O PC 104 A9 Data Bus IRQB L15 Out J9 IRQB Output IRQA L16 Out J7 IRQA Output CFG9 D11 In J10 Configuration Input CFG8 C11 In J10 Configuration Input CFG7 E11 In J10 Configuration Input CFG6 B11 In J10 Configuration Input CFG5 A11 In J10 Configuration In...

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