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dg_toeudp10gip_fpgasetup_intel.doc

26-Aug-20

Page 11

d. User enters

‘x’ to skip parameter setting for using default parameters to begin system

initialization, as shown in Figure 1-12. If user enters other keys, the menu for changing
parameter is displayed, similar to

“Reset TCPIP parameters” menu. The example

when running the main menu is described in

“dg_toe10gip_cpu_instruction” or

“dg_udp10gip_cpu_instruction” document.

Figure 1-12 Initialization complete

Note: Transfer performance in the demo depends on Test PC specification in Test platform.

Содержание TOE10G-IP

Страница 3: ...n Arria10 SoC Note Four LEDs are applied to show IP timeout status when the configuration file of the demo uses 1 hour timeout TOE10G IP UDP10G IP After running for 1 hour the IP stops the operation All LEDs are blinked to notify that the IP now is timeout User needs to reconfigure FPGA to restart the test ...

Страница 4: ...dg_toeudp10gip_fpgasetup_intel doc 26 Aug 20 Page 4 Figure 1 2 TOE10G IP UDP10G IP with CPU demo FPGA PC on Arria10 GX ...

Страница 5: ...dg_toeudp10gip_fpgasetup_intel doc 26 Aug 20 Page 5 Figure 1 3 TOE10G IP UDP10G IP with CPU demo FPGA PC on Cyclone10 GX ...

Страница 6: ...dg_toeudp10gip_fpgasetup_intel doc 26 Aug 20 Page 6 Figure 1 4 TOE10G IP UDP10G IP with CPU demo FPGA PC on Stratix10 GX ...

Страница 8: ...ammable clock to 322 265625 MHz by using Clock Control application as following step a Open Clock Controller application b Select Si5338 tab U50 and set CLK3 frequency 322 265625 MHz c Click Set button and wait until the application is active again d Close Clock controller application Figure 1 7 Reference clock programming ...

Страница 9: ...ware Setup to select USB BlasterII USB 1 b Click Auto Detect and select FPGA number c Select Arria 10 Cyclone 10 Stratix 10 device icon d Click Change File button select SOF file in pop up window and click open button e Check program f Click Start button to program FPGA g Wait until Progress status is equal to 100 Figure 1 8 FPGA Programmer ...

Страница 11: ...Figure 1 12 If user enters other keys the menu for changing parameter is displayed similar to Reset TCPIP parameters menu The example when running the main menu is described in dg_toe10gip_cpu_instruction or dg_udp10gip_cpu_instruction document Figure 1 12 Initialization complete Note Transfer performance in the demo depends on Test PC specification in Test platform ...

Страница 15: ...cable 2 command for FPGA 2 Figure 2 5 Run NiosII terminal on two consoles 5 Set the input to the console a Set 1 on Serial console of FPGA board 1 for running server mode b Set 0 on Serial console of FPGA board 2 for running client mode c Default parameters for server or client are displayed on the console as shown in Figure 2 6 Figure 2 6 Input mode ...

Страница 16: ...mode must be set before client mode When running TOE10G IP a Set parameters on server Serial console b Set parameters on client Serial console to start IP initialization by transferring ARP packet c After finishing initialization process IP initialization complete and main menu are displayed on server console and client console Figure 2 7 Main menu ...

Страница 17: ...arameters input x to skip parameter setting b For client mode user must change target port number Target FPGA to use same value as target port number FPGA Target c After finishing initialization process IP initialization complete and main menu are displayed on server console and client console Figure 2 8 Main menu of UDP10G IP ...

Страница 18: ...7 Mar 18 Add Part A FPGA PC test 1 2 4 Apr 18 Correct optical cable in Figures and the descriptions 1 3 5 Feb 19 Add Arria 10 GX board and change software to tcp_client_txrx_40G 1 4 31 May 19 Add timeout LED descriptions 1 5 20 Aug 19 Add Cyclone10 GX board 2 0 18 Jun 20 Remove test result on the console 3 0 26 Aug 20 TOE10G IP and UDP10G IP ...