DFI LANPARTY UT 915P-T12, Руководство пользователя

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BIOS Setup
select the best option in the “CAS Latency Time”
to “System Memory Frequency” fields.
3.1.3.2 CAS Latency Time
This field is used to select the latency between the DRAM read
command and the time that the data was received.
3.1.3.3 DRAM RAS# to CAS# Delay
This field is used to select the latency between the DRAM active
command and the read/write command.
3.1.3.4 DRAM RAS# Precharge
This field is used to select the idle clocks after issuing a precharge
command to the DRAM.
3.1.3.5 Precharge Delay (tRAS)
The options are Auto, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15.
3.1.3.6 System Memory Frequency
This field is used to select the memory clock speed of the DIMM.
Refer to chapter 1 (System Memory section) for detailed specifica-
tion of the memory supported by the system board.
3.1.3.7 SLP_S4# Assertion Width
The options are 1 to 2 Sec., 2 to 3 Sec., 3 to 4 Sec. and 4 to 5 Sec.
3.1.3.8 System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
3.1.3.9 Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache will
allow access to video BIOS addresssed at C0000H to C7FFFH to
be cached, if the cache controller is also enabled. The larger the range
of the Cache RAM, the faster the video performance.