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Award BIOS Setup Utility
SDRAM CAS Latency Time
The default setting is 3 which is 3 clock cycles for the CAS latency.
SDRAM Cycle Time Tras/Trc
This field selects the number of SCLKs for an access cycle. The
default is 6/8.
SDRAM RAS-to-CAS Delay
This field allows you to insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or
refreshed. This field applies only when synchronous DRAM is installed
in the system.
SDRAM RAS Precharge Time
If there is insufficient number of cycles for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data.
System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache will
allow access to video BIOS addresssed at C0000H to C7FFFH to
be cached, if the cache controller is also enabled. The larger the range
of the Cache RAM, the faster the video performance.
Memory Hole At 15M-16M
In order to improve system performance, certain space in memory can
be reserved for ISA cards. This memory must be mapped into the
memory space below 16MB. When enabled, the CPU assumes the 15-
16MB memory range is allocated to the hidden ISA address range
instead of the actual system DRAM. When disabled, the CPU assumes
