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Chapter 3 Hardware Installation

27

Chapter 3

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

AC/HAD_RST#

A30

O CMOS

3.3V Suspend/3.3V

Reset output to CODEC, active low.

AC/HDA_SYNC

A29

O CMOS

3.3V/3.3V

PD 1M

Sample-synchronization signal to the CODEC(s).

AC/HDA_BITCLK A32

I/O CMOS

3.3V/3.3V

Serial data clock generated by the external CODEC(s).

AC/HDA_SDOUT A33

O CMOS

3.3V/3.3V

Serial TDM data output to the CODEC.

AC/HDA_SDIN2

B28

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN1

B29

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN0

B30

I/O CMOS

3.3V Suspend/3.3V

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

GB

A13

I/O Analog

3.3V max Suspend

GBE0_MDI0-

A12

I/O Analog

3.3V max Suspend

GB

A10

I/O Analog

3.3V max Suspend

GBE0_MDI1-

A9

I/O Analog

3.3V max Suspend

GB

A7

I/O Analog

3.3V max Suspend

GBE0_MDI2-

A6

I/O Analog

3.3V max Suspend

GB

A3

I/O Analog

3.3V max Suspend

GBE0_MDI3-

A2

I/O Analog

3.3V max Suspend

GBE0_ACT#

B2

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 activity indicator, active low.

GBE0_LINK#

A8

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 link indicator, active low.

GBE0_LINK100# A4

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

GBE0_LINK1000# A5

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

GBE0_CTREF

A14

REF

GND min 3.3V max

N.C.

Reference voltage for Carrier Board Ethernet channel 0 magnetics center
tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V.

The reference voltage output shall be current limited on the Module. In
the case in which the reference

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

IDE_D0

D7

IDE_D1

C10

IDE_D2

C8

IDE_D3

C4

IDE_D4

D6

IDE_D5

D2

IDE_D6

C3

IDE_D7

C2

PD 10K

 to GND

IDE_D8

C6

IDE_D9

C7

IDE_D10

D3

IDE_D11

D4

IDE_D12

D5

IDE_D13

C9

IDE_D14

C12

IDE_D15

C5

IDE_A0

D13

IDE_A1

D14

IDE_A2

D15

IDE_IOW#

D9

O CMOS

3.3V / 3.3V

I/O write line to IDE device. Data latched on trailing (rising) edge.

IDE_IOR#

C14

O CMOS

3.3V / 3.3V

I/O read line to IDE device.

IDE_REQ

D8

I CMOS

3.3V / 5V

PD 5.6K

 to GND

IDE Device DMA Request. It is asserted by the IDE device to request a data transfer.

IDE_ACK#

D10

O CMOS

3.3V / 3.3V

IDE Device DMA Acknowledge.

IDE_CS1#

D16

O CMOS

3.3V / 3.3V

IDE Device Chip Select for 1F0h to 1FFh range.

IDE_CS3#

D17

O CMOS

3.3V / 3.3V

IDE Device Chip Select for 3F0h to 3FFh range.

IDE_IORDY

C13

I CMOS

3.3V / 5V

PU 4.7K

 to 3.3V

IDE device I/O ready input. Pulled low by the IDE device to extend the cycle.

IDE_RESET#

D18

O CMOS

3.3V / 3.3V

Reset output to IDE device, active low.

IDE_IRQ

D12

I CMOS

3.3V / 5V

PD 10K

 to GND

Interrupt request from IDE device.

IDE_CBLID#

D77

I CMOS

3.3V / 5V

Input from off-Module hardware indicating the type of IDE cable being
used. High indicates a 40-pin cable used for legacy IDE modes. Low
indicates that an 80-pin cable with interleaved grounds is used. Such a
cable is required for Ultra-DMA 66, 100 and 133 modes.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

S

A16

O SATA

AC coupled on Module

SATA0_TX-

A17

O SATA

AC coupled on Module

S

A19

I SATA

AC coupled on Module

SATA0_RX-

A20

I SATA

AC coupled on Module

S

B16

O SATA

AC coupled on Module

SATA1_TX-

B17

O SATA

AC coupled on Module

S

B19

I SATA

AC coupled on Module

SATA1_RX-

B20

I SATA

AC coupled on Module

S

A22

O SATA

AC coupled on Module

SATA2_TX-

A23

O SATA

AC coupled on Module

S

A25

I SATA

AC coupled on Module

SATA2_RX-

A26

I SATA

AC coupled on Module

S

B22

O SATA

AC coupled on Module

SATA3_TX-

B23

O SATA

AC coupled on Module

S

B25

I SATA

AC coupled on Module

SATA3_RX-

B26

I SATA

AC coupled on Module

ATA_ACT#

A28

I/O CMOS

3.3V / 3.3V

PU 10K

 to 3.3V

ATA (parallel and serial) or SAS activity indicator, active low.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

P

A68

PCIE_TX0-

A69

P

B68

PCIE_RX0-

B69

P

A64

PCIE_TX1-

A65

P

B64

PCIE_RX1-

B65

P

A61

PCIE_TX2-

A62

P

B61

PCIE_RX2-

B62

P

A58

PCIE_TX3-

A59

P

B58

PCIE_RX3-

B59

P

A55

PCIE_TX4-

A56

P

B55

PCIE_RX4-

B56

P

A52

PCIE_TX5-

A53

P

B52

PCIE_RX5-

B53

PCIE0 A88
PCIE0_CK_REF-

A89

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

D52

PEG_TX0-

D53

C52

PEG_RX0-

C53

D55

PEG_TX1-

D56

C55

PEG_RX1-

C56

D58

PEG_TX2-

D59

C58

PEG_RX2-

C59

D61

PEG_TX3-

D62

C61

PEG_RX3-

C62

D65

PEG_TX4-

D66

C65

PEG_RX4-

C66

D68

PEG_TX5-

D69

C68

PEG_RX5-

C69

D71

PEG_TX6-

D72

C71

PEG_RX6-

C72

D74

PEG_TX7-

D75

C74

PEG_RX7-

C75

D78

PEG_TX8-

D79

C78

PEG_RX8-

C79

D81

PEG_TX9-

D82

C81

PEG_RX9-

C82

P

D85

PEG_TX10-

D86

P

C85

PEG_RX10-

C86

P

D88

PEG_TX11-

D89

P

C88

PEG_RX11-

C89

P

D91

PEG_TX12-

D92

P

C91

PEG_RX12-

C92

P

D94

PEG_TX13-

D95

P

C94

PEG_RX13-

C95

P

D98

PEG_TX14-

D99

P

C98

PEG_RX14-

C99

P

D101

PEG_TX15-

D102

P

C101

PEG_RX15-

C102

PEG_LANE_RV#

D54

I CMOS

3.3V / 3.3V

PU 10K

 to 1.05V

PCI Express Graphics lane reversal input strap. Pull low on the Carrier
board to reverse lane order.

PEG_ENABLE#

D97

I CMOS

3.3V /3.3V

PU 10K

 to 3.3V

Strap to enable PCI Express x16 external graphics interface. Pull low to
enable the x16 PEG interface.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

EXCD0_CPPE#

A49

EXCD1_CPPE#

B48

EXCD0_PERST#

A48

EXCD1_PERST#

B47

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

PCI_AD0

C24

PCI_AD1

D22

PCI_AD2

C25

PCI_AD3

D23

PCI_AD4

C26

PCI_AD5

D24

PCI_AD6

C27

PCI_AD7

D25

PCI_AD8

C28

PCI_AD9

D27

PCI_AD10

C29

PCI_AD11

D28

PCI_AD12

C30

PCI_AD13

D29

PCI_AD14

C32

PCI_AD15

D30

PCI_AD16

D37

PCI_AD17

C39

PCI_AD18

D38

PCI_AD19

C40

PCI_AD20

D39

PCI_AD21

C42

PCI_AD22

D40

PCI_AD23

C43

PCI_AD24

D42

PCI_AD25

C45

PCI_AD26

D43

PCI_AD27

C46

PCI_AD28

D44

PCI_AD29

C47

PCI_AD30

D45

PCI_AD31

C48

PCI_C/BE0#

D26

PCI_C/BE1#

C33

PCI_C/BE2#

C38

PCI_C/BE3#

C44

PCI_DEVSEL#

C36

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

PCI bus Device Select, active low.

PCI_FRAME#

D36

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

PCI bus Frame control line, active low.

PCI_IRDY#

C37

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

PCI bus Initiator Ready control line, active low.

PCI_TRDY#

D35

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

PCI bus Target Ready control line, active low.

PCI_STOP#

D34

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

PCI bus STOP control line, active low, driven by cycle initiator.

PCI_PAR

D32

I/O CMOS

3.3V / 5V

PCI bus parity

PCI_PERR#

C34

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

Parity Error: An external PCI device drives PERR# when it receives data that has a parity error.

PCI_REQ0#

C22

PU 8.2K

to 3.3V

PCI_REQ1#

C19

PU 8.2K

to 3.3V

PCI_REQ2#

C17

PU 8.2K

to 3.3V

PCI_REQ3#

D20

PU 8.2K

to 3.3V

PCI_GNT0#

C20

PCI_GNT1#

C18

PCI_GNT2#

C16

PCI_GNT3#

D19

PCI_RESET#

C23

O CMOS

3.3V Suspend/ 5V

PCI Reset output, active low.

PCI_LOCK#

C35

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

PCI Lock control line, active low.

PCI_SERR#

D33

I/O OD CMOS 3.3V / 5V

PU 8.2K

to 3.3V

System Error: SERR# may be pulsed active by any PCI device that detects a system error condition.

PCI_PME#

C15

I CMOS

3.3V Suspend/ 5V

PU 10K

 to 3.3VSB PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1–S5.

PCI_CLKRUN#

D48

I/O CMOS

3.3V / 5V

PU 8.2K

to 3.3V

Bidirectional pin used to support PCI clock run protocol for mobile systems.

PCI_IRQA#

C49

PU 8.2K

to 3.3V

PCI_IRQB#

C50

PU 8.2K

to 3.3V

PCI_IRQC#

D46

PU 8.2K

to 3.3V

PCI_IRQD#

D47

PU 8.2K

to 3.3V

PCI_CLK

D50

O CMOS

3.3V / 3.3V

PCI 33MHz clock output.

PCI_M66EN

D49

I CMOS

3.3V / 5V

PD 10K

 to GND

Module input signal indicates whether an off-Module PCI device is
capable of 66MHz operation. Pulled to GND by Carrier Board device or
by Slot Card if the devices are NOT capable of 66 MHz operation.
If the Module is not capable of supporting 66 MHz PCI operation, this

input may be a no-connect on the Module.
If the Module is capable of supporting 66 MHz PCI operation, and if this

input is held low by the Carrier Board, the Module PCI interface shall
operate at 33 MHz.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

USB0+

A46

USB0-

A45

USB1+

B46

USB1-

B45

USB2+

A43

USB2-

A42

USB3+

B43

USB3-

B42

USB4+

A40

USB4-

A39

USB5+

B40

USB5-

B39

USB6+

A37

USB6-

A36

USB7+

B37

USB7-

B36

USB_0_1_OC#

B44

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_2_3_OC#

A44

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

USB over-current sense, USB channels 2 and 3. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not

pull this line high on the Carrier Board.

USB_4_5_OC#

B38

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

USB over-current sense, USB channels 4 and 5. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_6_7_OC#

A38

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

USB over-current sense, USB channels 6 and 7. A pull-up for this line
shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

A71

LVDS_A0-

A72

A73

LVDS_A1-

A74

A75

LVDS_A2-

A76

A78

LVDS_A3-

A79

LV

A81

LVDS_A_CK-

A82

B71

LVDS_B0-

B72

B73

LVDS_B1-

B74

B75

LVDS_B2-

B76

B77

LVDS_B3-

B78

LV

B81

LVDS_B_CK-

B82

LVDS_VDD_EN

A77

O CMOS

3.3V / 3.3V

PD 100K

 to GND

LVDS panel power enable

LVDS_BKLT_EN

B79

O CMOS

3.3V / 3.3V

PD 100K

 to GND

LVDS panel backlight enable

LVDS_BKLT_CTRL B83

O CMOS

3.3V / 3.3V

PD 100K

 to GND

LVDS panel backlight brightness control

LVDS_I2C_CK

A83

I/O OD CMOS 3.3V / 3.3V

PU 2.2K

 to 3.3V

I2C clock output for LVDS display use

LVDS_I2C_DAT

A84

I/O OD CMOS 3.3V / 3.3V

PU 2.2K

 to 3.3V

I2C data line for LVDS display use

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

LPC_AD0

B4

LPC_AD1

B5

LPC_AD2

B6

LPC_AD3

B7

LPC_FRAME#

B3

O CMOS

3.3V / 3.3V

LPC frame indicates the start of an LPC cycle

LPC_DRQ0#

B8

LPC_DRQ1#

B9

LPC_SERIRQ

A50

I/O CMOS

3.3V / 3.3V

PU 10K

to 3.3V

LPC serial interrupt

LPC_CLK

B10

O CMOS

3.3V / 3.3V

LPC clock output - 33MHz nominal

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

SPI_CS#

B97

O CMOS

3.3V Suspend/3.3V

Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1

SPI_MISO

A92

I CMOS

3.3V Suspend/3.3V

Data in to Module from Carrier SPI

SPI_MOSI

A95

O CMOS

3.3V Suspend/3.3V

Data out from Module to Carrier SPI

SPI_CLK

A94

O CMOS

3.3V Suspend/3.3V

Clock from Module to Carrier SPI

SPI_POWER

A91

O

3.3V Suspend/3.3V

Power supply for Carrier Board SPI – sourced from Module – nominally

3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier

BIOS_DIS0#

A34

BIOS_DIS1#

B88

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

VGA_RED

B89

O Analog

Analog

PD 150

Red for monitor. Analog output

VGA_GRN

B91

O Analog

Analog

PD 150

Green for monitor. Analog output

VGA_BLU

B92

O Analog

Analog

PD 150

Blue for monitor. Analog output

VGA_HSYNC

B93

O CMOS

3.3V / 3.3V

Horizontal sync output to VGA monitor

VGA_VSYNC

B94

O CMOS

3.3V / 3.3V

Vertical sync output to VGA monitor

VGA_I2C_CK

B95

I/O OD CMOS 3.3V / 3.3V

PU 2.2K

 to 3.3V

DDC clock line (I2C port dedicated to identify VGA monitor capabilities)

VGA_I2C_DAT

B96

I/O OD CMOS 3.3V / 3.3V

PU 2.2K

 to 3.3V

DDC data line.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

I2C_CK

B33

I/O OD CMOS 3.3V Suspend/3.3V

PU 2.2K

 to 3.3VSB General purpose I2C port clock output

I2C_DAT

B34

I/O OD CMOS 3.3V Suspend/3.3V

PU 2.2K

 to 3.3VSB General purpose I2C port data I/O line

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

SPKR

B32

O CMOS

3.3V / 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems.

This port provides the PC beep signal and is mostly intended for
debugging purposes.

WDT

B27

O CMOS

3.3V / 3.3V

Output indicating that a watchdog time-out event has occurred.

KBD_RST#

A86

I CMOS

3.3V / 3.3V

PU 10K

 to 3.3V

Input to Module from (optional) external keyboard controller that can force a reset. Pulled high on the Module. This is a legacy
artifact of the PC-AT.

KBD_A20GATE

A87

I CMOS

3.3V / 3.3V

PU 10K

 to 3.3V

Input to Module from (optional) external keyboard controller that can be used to control the CPU A20 gate line. The A20GATE
restricts the memory access to the bottom megabyte and is a legacy artifact of the PC-AT.Pulled high on the Module.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

PWRBTN#

B12

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,

as well as powering the system down.

SYS_RESET#

B49

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

Reset button input. Active low request for Module to reset and reboot.

May be falling edge sensitive. For situations when SYS_RESET# is

not able to reestablish control of the system, PWR_OK or a power
cycle may be used.

CB_RESET#

B50

O CMOS

3.3V Suspend/3.3V

PD 100K

 to GND

Reset output from Module to Carrier Board. Active low. Issued by

Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum

specification, a watchdog timeout, or may be initiated by the Module
software.

PWR_OK

B24

I CMOS

3.3V / 3.3V

Power OK from main power supply. A high value indicates that the

power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.

SUS_STAT#

B18

O CMOS

3.3V Suspend/3.3V

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3#

A15

O CMOS

3.3V Suspend/3.3V

Indicates system is in Suspend to RAM state. Active low output. An

inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.

SUS_S4#

A18

O CMOS

3.3V Suspend/3.3V

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

A24

O CMOS

3.3V Suspend/3.3V

Indicates system is in Soft Off state.

WAKE0#

B66

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB PCI Express wake up signal.

WAKE1#

B67

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB General purpose wake up signal. May be used to implement wake-up

on PS2 keyboard or mouse activity.

BATLOW#

A27

I CMOS

3.3V Suspend/ 3.3V

PU 10K

 to 3.3VSB

Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

THRM#

B35

I CMOS

3.3V / 3.3V

PU 10K

 to 3.3V

Input from off-Module temp sensor indicating an over-temp situation.

THRMTRIP#

A35

O CMOS

3.3V / 3.3V

PU 10K

 to 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

SMB_CK

B13

I/O OD CMOS 3.3V Suspend/3.3V

PU 2.2K

 to 3.3VSB System Management Bus bidirectional clock line.

SMB_DAT

B14

I/O OD CMOS 3.3V Suspend/3.3V

PU 2.2K

 to 3.3VSB System Management Bus bidirectional data line.

SMB_ALERT#

B15

I CMOS

3.3V Suspend/3.3V

PU 10K

 to 3.3VSB

System Management Bus Alert – active low input can be used to
generate an SMI# (System Management Interrupt) or to wake the system.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

GPO0

A93

GPO1

B54

GPO2

B57

GPO3

B63

GPI0

A54

GPI1

A63

GPI2

A67

GPI3

A85

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

VCC_12V

A104~A109
B104~B109
C104~C109

D104~D109

Power

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

VCC_5V_SBY

B84~B87

Power

Standby power input: +5.0V nominal. If VCC5_SBY is used, all
available VCC_5V_SBY pins on the connector(s) shall be used. Only
used for standby and suspend functions. May be left unconnected if

these functions are not used in the system design.

VCC_RTC

A47

Power

Real-time clock circuit-power input. Nom3.0V.

GND

A1, A11, A21, A31, A41,
A51, A57, A60, A66, A70,
A80, A90, A96,A100,
A110, B1, B11, B21 ,B31,

B41, B51, B60, B70, B80,
B90, B100, B110, C1,C11,
C21, C31, C41, C51, C60,
C70, C76, C80, C84, C87,
C90, C93, C96, C100,
C103, C110, D1,D11,D21,

D31, D41, D51, D60,
D67, D70,D76, D80, D84,
D87, D90, D93, D96,
D100 D103 D110

Power

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to Carrier
Board GND plane.

Signal

Pin#

Pin Type

Pwr Rail /Tolerance

PU/PD

Description

TYPE0#

C54

PDS

TYPE1#

C57

PDS

TYPE2#

D57

PDS

TYPE10#

A97

PDS

TYPE 10#
NC pin out R2.0
PD pin out Type 10 pull down to ground with 47K resistor
12V pin out R1.0
A carrier can detect a R1.0 Module by the presence of 12V on this pin. R2.0 Module types 1-6 will no connet this pin. Type 10
Modules shall pull this pin to ground through a 4.7K resistor.

Pin Types
I      Input to the Module
O     Output from the Module
I/O   Bi-directional input / output signal
OD   Open drain output

IDE Signals Descriptions

I/O CMOS

3.3V / 5V

Bidirectional data to / from IDE device.

O CMOS

3.3V / 3.3V

Address lines to IDE device.

AC97/HDA Signals Descriptions

Serial TDM data inputs from up to 3 CODECs.

Gigabit Ethernet Signals Descriptions

Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec

modes. Some pairs are unused in some modes, per the following:
                                             1000BASE-T   100BASE-TX   10BASE-T
                       MDI[0]+/-      B1_DA+/-        TX+/-               TX+/-

                       MDI[1]+/-      B1_DB+/-        RX+/-               RX+/-
                       MDI[2]+/-      B1_DC+/-
                       MDI[3]+/-      B1_DD+/-

Serial ATA or SAS Channel 1 receive differential pair.

Serial ATA or SAS Channel 2 transmit differential pair.

Serial ATA or SAS Channel 2 receive differential pair.

SATA Signals Descriptions

Serial ATA or SAS Channel 0 transmit differential pair.

Serial ATA or SAS Channel 0 receive differential pair.

Serial ATA or SAS Channel 1 transmit differential pair.

Serial ATA or SAS Channel 3 transmit differential pair.

Serial ATA or SAS Channel 3 receive differential pair.

PCI Express Lanes Signals Descriptions

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 0

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 1

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 2

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 0

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 1

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 3

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 4

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 2

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 3

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 5

O PCIE

PCIE

Reference clock output for all PCI Express and PCI Express Graphics lanes.

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 4

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 5

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 1

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 1

PEG Signals Descriptions

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 0

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 3

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 3

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 2

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 2

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 5

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 5

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 4

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 4

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 7

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 7

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 6

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 6

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 9

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 8

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 8

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 11

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 11

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 10

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 13

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 12

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 15

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 15

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 14

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 14

ExpressCard Signals Descriptions

I CMOS

3.3V /3.3V

PU 10K

 to 3.3V

PCI ExpressCard: PCI Express capable card request, active low, one per card

O CMOS

3.3V /3.3V

PCI ExpressCard: reset, active low, one per card

I CMOS

3.3V / 5V

PCI bus master request input lines, active low.

O CMOS

3.3V / 5V

PCI bus master grant output lines, active low.

PCI Signals Descriptions

I/O CMOS

3.3V / 5V

PCI bus multiplexed address and data lines

I/O CMOS

3.3V / 5V

PCI bus byte enable lines, active low

I/O USB

3.3V Suspend/3.3V

USB differential pairs 1

I/O USB

3.3V Suspend/3.3V

USB differential pairs 2

I CMOS

3.3V / 5V

PCI interrupt request lines.

USB Signals Descriptions

I/O USB

3.3V Suspend/3.3V

USB differential pairs 0

I/O USB

3.3V Suspend/3.3V

USB differential pairs 5

I/O USB

3.3V Suspend/3.3V

USB differential pairs 6

I/O USB

3.3V Suspend/3.3V

USB differential pairs 3

I/O USB

3.3V Suspend/3.3V

USB differential pairs 4

LVDS Channel B differential clock

LPC Signals Descriptions

I/O USB

3.3V Suspend/3.3V

USB differential pairs 7, USB7 may be configured as a USB client or as a host, or both, at the
Module designer's discretion.(CR900-B default set as a host)

LVDS Signals Descriptions

O LVDS

LVDS

LVDS Channel A differential pairs

O LVDS

LVDS

O LVDS

LVDS

O LVDS

LVDS

I/O CMOS

3.3V / 3.3V

LPC multiplexed address, command and data bus

LVDS Channel A differential clock

O LVDS

LVDS

LVDS Channel B differential pairs

O LVDS

LVDS

O LVDS

LVDS

O LVDS

LVDS

O LVDS

LVDS

O LVDS

LVDS

I CMOS

3.3V / 3.3V

LPC serial DMA request

SPI Signals Descriptions

I CMOS

 NA

Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options of BIOS disable signals.

Module type Signal Descriptions

TYPE2#    TYPE1#   TYPE0#
    X              X             X          pin out Type 1
   NC           NC          NC         pin out Type 2
   NC           NC          GND      pin out Type 3 (no IDE)
   NC           GND       NC         pin out Type 4 (no PCI)
   NC           GND       GND      pin out Type 5 (no IDE, no PCI)
  GND          NC           NC       pin out Type 6 (no IDE, no PCI)

I CMOS

3.3V Suspend / 3.3V

General purpose input pins.

Power and GND Signal Descriptions

VGA Signals Descriptions

I2C BUS Signal Descriptions

Power and System Management Signals Descriptions

GPIO Signals Descriptions

O CMOS

3.3V / 3.3V

General purpose output pins.

Miscellaneous Signal Descriptions

Thermal Protectiont Signals Descriptions

SM Bus Signals Descriptions

Содержание CR900-B

Страница 1: ...www dfi com Chapter 1 Introduction 1 CR900 B COM Express Basic Module User s Manual A20520442...

Страница 2: ...the party responsible for compli ance could void the user s authority to operate the equipment 2 Shielded interface cables must be used in order to comply with the emission limits Copyright This publi...

Страница 3: ...anical Diagram 11 System Memory 12 Installing the DIMM Module 13 CPU 14 Connectors 15 CPU Fan Connector 15 COM Express Connectors 16 COM Express connector Signal Discription 18 Standby Power LED 29 Co...

Страница 4: ...ur system unit Static electrical discharge can damage computer components without causing any signs of physical damage You must take extra care in han dling them to ensure against electrostatic build...

Страница 5: ...rmation listed above This may differ in accordance with the sales region or models in which it was sold For more information about the standard package in your region please contact your dealer or sal...

Страница 6: ...hnology Intel Core i7 3610QE 6M Cache up to 3 3 GHz 45W Intel Core i5 3610ME 3M Cache up to 3 3 GHz 35W Intel Core i3 3120ME 3M Cache 2 4 GHz 35W 2nd Generation Intel CoreTM processors 32nm process te...

Страница 7: ...ent blend of graphics performance and features to meet business needs It provides excellent video and 3D graphics with out standing graphics responsiveness These enhancements deliver the performance a...

Страница 8: ...he different types of COM Express modules CR900 B is a COM Express Basic module The dimension is 95mm x 125mm 106 00 91 00 70 00 51 00 4 00 18 00 6 00 0 00 16 50 4 00 0 00 Extended Basic Compact Mini...

Страница 9: ...2 IDE PCI Min Max DFI CR900 B Type 2 C D PCI Express Lanes 16 31 0 16 0 PCI Express Graphics PEG 0 1 1 Muxed SDVO Channels 1 2 0 2 0 PCI Express Lanes 6 15 NA NA PCI Bus 32 Bit 1 1 1 PATA Port 1 1 1 L...

Страница 10: ...annel 2nd SPI Bus 2nd Generation Intel Core i7 i5 i3 Intel Celeron CORE Processor CORE CORE CORE Graphics CORE Memory Controller DMI x4 Direct Media Interface Intel FDI Flexible Display Interface DDR3...

Страница 11: ...Bottom View 2 70 7 pcs Bottom View Top View 0 00 0 00 2 00 14 00 12 50 70 20 0 00 0 00 76 00 117 00 0 00 4 00 121 00 4 00 4 00 37 41 43 67 87 00 91 00 4 00 0 00 87 00 87 00 121 00 117 00 91 00 125 00...

Страница 12: ...your board processor disk drives add in boards and other components Perform installation procedures at an ESD workstation only If such a station is not available you can provide some ESD protection b...

Страница 13: ...board 4 Note the key on the socket The key ensures the module can be plugged into the socket in only one direction 6 Push down the module until the clips at each end of the socket lock into position Y...

Страница 14: ...ew is in its unlock position If it s not use a screwdriver to turn the screw to its unlock position Screw in unlocked position 5 Position the CPU above the socket The gold triangular mark on the CPU m...

Страница 15: ...BIOS will display the cur rent speed of the cooling fan Refer to chapter 3 of the manual for more information 3 1 Sense Power Ground COM Express Connectors The COM Express connectors are used to inter...

Страница 16: ...www dfi com Chapter 3 Hardware Installation 16 Chapter 3 COM Express Connectors...

Страница 17: ...www dfi com Chapter 3 Hardware Installation 17 Chapter 3...

Страница 18: ...CMOS 3 3V 3 3V I O read line to IDE device IDE_REQ D8 I CMOS 3 3V 5V PD 5 6K to GND IDE Device DMA Request It is asserted by the IDE device to request a data transfer IDE_ACK D10 O CMOS 3 3V 3 3V IDE...

Страница 19: ...C coupled on Module SATA0_TX A17 O SATA AC coupled on Module SATA0_RX A19 I SATA AC coupled on Module SATA0_RX A20 I SATA AC coupled on Module SATA1_TX B16 O SATA AC coupled on Module SATA1_TX B17 O S...

Страница 20: ...s Descriptions Serial ATA or SAS Channel 0 transmit differential pair Serial ATA or SAS Channel 0 receive differential pair Serial ATA or SAS Channel 1 transmit differential pair Serial ATA or SAS Cha...

Страница 21: ...2 O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 3 I PCIE AC coupled off Module PCI Express Differential Receive Pairs 5 O PCIE PCIE Reference clock output for all PCI Express and...

Страница 22: ...s Graphics receive differential pairs 15 O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 14 I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 14...

Страница 23: ...used to support PCI clock run protocol for mobile systems PCI_IRQA C49 PU 8 2K to 3 3V PCI_IRQB C50 PU 8 2K to 3 3V PCI_IRQC D46 PU 8 2K to 3 3V PCI_IRQD D47 PU 8 2K to 3 3V PCI_CLK D50 O CMOS 3 3V 3...

Страница 24: ...D28 PCI_AD12 C30 PCI_AD13 D29 PCI_AD14 C32 PCI_AD15 D30 PCI_AD16 D37 PCI_AD17 C39 PCI_AD18 D38 PCI_AD19 C40 PCI_AD20 D39 PCI_AD21 C42 PCI_AD22 D40 PCI_AD23 C43 PCI_AD24 D42 PCI_AD25 C45 PCI_AD26 D43 P...

Страница 25: ...ock from Module to Carrier SPI SPI_POWER A91 O 3 3V Suspend 3 3V Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POWER Carriers...

Страница 26: ...il Tolerance PU PD Description PWRBTN B12 I CMOS 3 3V Suspend 3 3V PU 10K to 3 3VSB A falling edge creates a power button event Power button events can be used to bring a system out of S5 soft off and...

Страница 27: ...Indicates imminent suspend operation used to notify LPC devices SUS_S3 A15 O CMOS 3 3V Suspend 3 3V Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the Carr...

Страница 28: ...gement Bus Alert active low input can be used to generate an SMI System Management Interrupt or to wake the system Signal Pin Pin Type Pwr Rail Tolerance PU PD Description GPO0 A93 GPO1 B54 GPO2 B57 G...

Страница 29: ...tandby mode Cooling Option Heat Sink with Cooling Fan 1 2 and 3 denote the locations of the thermal pads designed to contact the corresponding components that are on CR900 B Top View of the Heat Sink...

Страница 30: ...he mounting hole of the heatsink with the mounting hole of the module and then from the bottom side of the module secure them with the provided screw The module and heatsink as sembly should look like...

Страница 31: ...ide of the board with the screws already fixed in place Bolts Mounting screw 6 The photo below shows the component side of the board with the bolts already fixed in place 7 Position the heat sink on t...

Страница 32: ...igned with the bolts on the carrier board This will also align the COM Express connectors of the two boards to each other COM Express connec tors on CR900 B COM Express connectors on the carrier board...

Страница 33: ...Utility The BIOS Setup Utility can only be operated from the keyboard and all commands are key board commands The commands are available at the right side of each setup screen The BIOS Setup Utility d...

Страница 34: ...tion Set the date Use Tab to switch between date elements Aptio Setup Utility Copyright C 2011 American Megatrends Inc Save Exit Chipset Version 2 14 1219 Copyright C 2011 American Megatrends Inc Sele...

Страница 35: ...American Megatrends Inc Version 2 14 1219 Copyright C 2011 American Megatrends Inc ACPI Settings Enable ACPI Auto Configuration ACPI Sleep State Resume by PME Resume by RTC Alarm Advanced Disabled S3...

Страница 36: ...Version 2 14 1219 Copyright C 2011 American Megatrends Inc System Hardware Monitor CPU Smart Fan CPU Temperature CPU FAN Speed VCore Vgfx DDR 1 05V CPU VCCSA Advanced Enabled 49 C 4968 RPM 0 912 V 1...

Страница 37: ...n Up Device Serial ATA Port 2 Software Preserve Port 2 Hot Plug External SATA Spin Up Device Serial ATA Port 3 Software Preserve Port 3 Hot Plug External SATA Spin Up Device Serial ATA Port 4 Software...

Страница 38: ...l Sku Firmware 5MB Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults ESC Exit Aptio Setup Utility Copyright C 2011 American Megatrends Inc Vers...

Страница 39: ...1219 Copyright C 2011 American Megatrends Inc SATA Port 0 SATA Port 1 ATA Controller Advanced Not Present Not Present IDE Mode Select Screen Select Item Enter Select Change Opt F1 General Help F2 Prev...

Страница 40: ...ends Inc WatchDog1 function WatchDog2 function Advanced Disabled Disabled Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults ESC Exit Chipset Co...

Страница 41: ...Inc Version 2 14 1219 Copyright C 2011 American Megatrends Inc Intel PCH RC Version Intel PCH SKU Name Intel PCH Rev ID PCI Express Configuration PCH Azalia Configuration PCH LAN Controller Wake on LA...

Страница 42: ...bled Chipset Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults ESC Exit Control detection of the Azalia device Disable Azalia will be unconditi...

Страница 43: ...ure size 128MB or 256MB or 512MB DVMT Pre Allocated Select DVMT 5 0 Pre Allocated Fixed Graphics Memory size used by the Internal Graphics Device Gfx Low Power Mode This option is applicable for SFF o...

Страница 44: ...33 Mhz 4096 MB DDR3 Not Present 4096 MB DDR3 9 9 9 24 DDR3 Chipset Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults ESC Exit PEG bifurcation c...

Страница 45: ...ord Sets the user password Set Administrator Password Aptio Setup Utility Copyright C 2011 American Megatrends Inc Version 2 14 1219 Copyright C 2011 American Megatrends Inc Password Description If ON...

Страница 46: ...alog box will appear Select Yes to save values as user default Restore User Defaults To restore user default to all the setup options select this field and then press En ter A dialog box will appear S...

Страница 47: ...ne done done done done done After finishing BIOS update please turn off the AC power Wait about 10 seconds and then turn on the AC power again Clear Administrator or User Password If you forgot the ad...

Страница 48: ...and cannot be used to replace one which has been utilized on other system boards 3 If you do not follow the methods above the Intel Management Engine will not be updated and will cease to be effectiv...

Страница 49: ...required to enhance the performance of the system board Insert the CD into a CD ROM drive The autorun screen Mainboard Utility CD will appear If after inserting the CD Autorun did not automatically s...

Страница 50: ...Framework 3 5 make sure you have updated your Windows XP operating system to Service Pack 3 To install the driver click Microsoft NET Framework 3 5 on the main menu 1 Read the license agreement care f...

Страница 51: ...To install the utility click Intel Chipset Device Software on the main menu 1 Setup is ready to install the utility Click Next 2 Read the license agreement then click Yes 1 Click I accept the agreemen...

Страница 52: ...install the driver click Intel HD Graphics Drivers on the main menu 1 Setup is now ready to install the graphics driver Click Next By default the Automatically run WinSAT and enable the Windows Aero d...

Страница 53: ...xt to continue 3 Go through the readme docu ment for system requirements and installation tips then click Next 2 Read the license agreement then click Yes 5 Click Yes I want to restart this computer n...

Страница 54: ...ers make sure you have installed Microsoft NET Framework 3 5 SP1 To install the driver click Intel HD Graphics Drivers on the main menu 4 Setup is currently installing the driver After installation ha...

Страница 55: ...l the driver click Intel Management Engine Drivers on the main menu 1 Setup is ready to install the driver Click Next 2 Read the license agreement then click Yes 3 Setup is currently installing the dr...

Страница 56: ...y to install the driver Click Install Drivers and Sofeware 3 Click I accept the terms in the li cense agreement then click Next 2 Setup is now ready to install the LAN driver Click Next 5 Click Instal...

Страница 57: ...lick I accept the terms in the license agreement and then click Next 1 Setup is ready to install the DFI Utility drifer Click Next Note If you are using Windows 7 you need to access the operating syst...

Страница 58: ...Rapid Storage Technology is a utility that allows you to monitor the current status of the SATA drives It enables enhanced performance and power management for the storage subsystem To install the dr...

Страница 59: ...ick Next 5 Setup is now installing the utility Click Next to continue 3 Read the license agreement then click Yes 6 Click Yes I want to restart my computer now then click Finish Restarting the system...

Страница 60: ...software installation 2 Click Next 3 Read the license agreement and then click I accept the terms in the license agreement Click Next Infineon TPM Driver and Tool optional To install the driver click...

Страница 61: ...5 Supported Software 61 Chapter 5 4 Enter the necessary information and then click Next 5 Select a setup type and then click Next 4 Click Install 5 The setup program is currently installing the softw...

Страница 62: ...install the driver click Audio Drivers for COM330 B Carrier Board on the main menu F6 Floppy This is used to create a floppy driver diskette needed when you install Windows XP using the F6 installatio...

Страница 63: ...Adobe Acrobat Reader 9 3 To install the reader click Adobe Acrobat Reader 9 3 on the main menu 1 Click Next to install or click Change Destination Folder to select another folder 2 Click Install to b...

Страница 64: ...te http www nliteos com download html 2 Install nLite Important Due to it s coding with Visual Net you may need to first install NET Framework prior to installing nLite 3 Download relevant RAID AHCI d...

Страница 65: ...table ISO Click Next 9 Click Insert and then select Multiple driver folder to select the drivers you will integrate Click Next 10 Select only the drivers ap propriate for the Windows version that you...

Страница 66: ...e uncertain of the southbridge chip used on your motherboard select all RAID AHCI controllers and then click OK 12 Click Next 13 The program is currently integrating the drivers and applying changes t...

Страница 67: ...16 Or you can choose to burn it directly to a disc by selecting the Direct Burn mode under the General section Select the optical device and all other necessary settings and then click Next 17 You hav...

Страница 68: ...ted by the motherboard chip set from Intel s website Transfer the downloaded driver files to C AHCI 4 Open Device Manager and right click on one of the Intel Serial ATA Storage Con trollers then selec...

Страница 69: ...1 A warning message appeared because the selected SATA controller did not match your hardware device Ignore the warning and click Yes to proceed 12 Click Finish 13 The system s settings have been chan...

Страница 70: ...int count_L Set Count WriteEC 0xB7 count_H High Byte WriteEC 0xB8 count_L Low Byte Enable Watch Dog Timer WriteEC 0xB4 0x02 int GetWDTime void int sum data_h data_l Select EC Read Type outportb EC_En...

Страница 71: ...Y HAS FAILED The CMOS battery is no longer functional It should be replaced Important Danger of explosion if battery incorrectly replaced Replace only with the same or equivalent type recommended by t...

Страница 72: ...or s power switch is on 2 Check that one end of the monitor s power cord is properly attached to the monitor and the other end is plugged into a working AC outlet If necessary try another outlet 3 Che...

Страница 73: ...attaching it to a serial port that is work ing and configured correctly If the serial device does not work either the cable or the serial device has a problem If the serial device works the problem ma...

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