26
Chapter 2
HARDWARE INSTALLATION
User's Manual |
CMS631
LPC Connector
X
Internal I/O Connectors
1
M.2 E Key
2230
(Opt.)
M.2 M Key
M.2 M Key
DDR4_1
DDR4_2
DDR4_3
DDR4_4
Socket LGA1151
+12V Power
4
8
1
5
CPU FAN
1
Battery
JP11/12/13/14/15
PCI 2
PCI 5
6
2
6
2
6
5
1
6
5
2
1
JP1
JP2
2
JP4
JP3
1
S/PDIF
2
9
10
1
Front Audio
6
5
2
1
JP8
JP10
JP6
1
9
2
1
9
2
COM4
COM2
COM3
Buzzer
1
2
10
USB2_
9/14
1
2
7
8
1
13
12
24
ATX Power
1
2
11
Front
Panel
LAN LED
SPI Flash
BIOS
1
1
PCIe 1 (PCIe x16)
Digital I/O
JP7
1
System
Fan 1
1
System Fan 3
SATA 1
(R1)
SATA 0
(R0)
SATA 3
(R3)
SATA 2
(R2)
Mic-in
Line-out
Line-in (opt.)
VGA
COM 1
HDMI
DP++
LAN 2
USB3_1/2
USB2_1/2
LAN 1
USB3_3/4
USB2_3/4
USB7/8
Intel
Q470E/H420E
LPC
14
2
13
1
5
1
5
1
PCIe 2 (PCIe x4)
6
5
2
1
J12
1 1 1 1 1
DIO
Power
USB2_10
System Fan 2
1
9
2
6
5
2
1
6
5
2
1
6
5
2
1
1
JP5
(Clear CMOS)
USB2_5/6
USB3_5/6
USB2
11/12
1
1
1
1
SDJ2
1
6
CN37
PCI 1
PCI 3
PCI 4
1
9
2
1
9
2
COM5 COM6
SATA 5
(R5)
SATA 4
(R4)
1
10
2
1
10
11
1
PS2
1
JP27
1
JP28
1
JP26
1
JP23
JP24
1
20
10
11
13
14
1
2
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s transi-
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the
pin functions of the LPC connector.
Pin Assignment
Pin Assignment
1
CLK
2
L_AD1
3
RST#
4
L_AD0
5
FRAME#
6
VCC3
7
LAD3
8
GND
9
LAD2
10
---
11
SERIRQ
12
GND
13
5V5B
14
5V
