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Award BIOS Setup Utility
SDRAM Cycle Length
This field is used to set the clock cycle for the CAS latency.
Bank Interleave
The options are Disabled, 2 Bank and 4 Bank.
Memory Hole
This field is used to select the memory area that must not be
addressed to the ISA bus.
P2C/C2P Concurrency
When enabled, the PCI/AGP master to CPU cycle will be concurrent
whenever the Host CPU is performing R/W access to the PCI or
slave devices.
Fast R-W Turn Around
When enabled, the turn around time of a memory read followed by
a memory write is reduced.
System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
Video RAM Cacheable
When enabled, it allows the video RAM to be cacheable thus providing
better video performance. If your graphics card does not support this
function, leave this field in its default setting - Disabled.
