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Chapter 3 Hardware Installation

Chapter 3

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

AC/HAD_RST#

A30

O CMOS

3.3V Suspend/3.3V

Connect to CODEC pin 11 RESET#

Reset output to CODEC, active low.

AC/HDA_SYNC

A29

O CMOS

3.3V/3.3V

Connect to CODEC pin 10 SYNC

Sample-synchronization signal to the CODEC(s).

AC/HDA_BITCLK

A32

I/O CMOS

3.3V/3.3V

Connect to CODEC pin 6 BIT_CLK

Serial data clock generated by the external CODEC(s).

AC/HDA_SDOUT

A33

O CMOS

3.3V/3.3V

Connect to CODEC pin 5 SDATA_OUT

Serial TDM data output to the CODEC.

AC/HDA_SDIN2

B28

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN1

B29

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN0

B30

I/O CMOS

3.3V Suspend/3.3V

Connect 33

Ω

in series to CODEC0 pin 8 SDATA_IN

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A13

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI0+/-

Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec

modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T

                       MDI[0]+/-      B1_DA+/-        TX+/-               TX+/-
                       MDI[1]+/-      B1_DB+/-        RX+/-               RX+/-
                       MDI[2]+/-      B1_DC+/-

MDI[3]+/- B1_DD+/-

GBE0_MDI0-

A12

I/O Analog

3.3V max Suspend

A10

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI1+/-

GBE0_MDI1-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI2+/-

GBE0_MDI2-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI3+/-

GBE0_MDI3-

I/O Analog

3.3V max Suspend

GBE0_ACT#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 activity indicator, active low.

GBE0_LINK#

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 link indicator, active low.

GBE0_LINK100#

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

GBE0_LINK100#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

GBE0_LINK1000#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA0_TX-

A17

O SATA

AC coupled on Module

AC Coupling capacitor

A19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA0_RX-

A20

I SATA

AC coupled on Module

AC Coupling capacitor

B16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA1_TX-

B17

O SATA

AC coupled on Module

AC Coupling capacitor

B19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA1_RX-

B20

I SATA

AC coupled on Module

AC Coupling capacitor

A22

O SATA

AC coupled on Module

SATA2_TX-

A23

O SATA

AC coupled on Module

A25

I SATA

AC coupled on Module

SATA2_RX-

A26

I SATA

AC coupled on Module

B22

O SATA

AC coupled on Module

SATA3_TX-

B23

O SATA

AC coupled on Module

B25

I SATA

AC coupled on Module

SATA3_RX-

B26

I SATA

AC coupled on Module

ATA_ACT#

A28

I/O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Connect to LED and

recommend

current limit resistor 220

Ω

to 3.3V

ATA (parallel and serial) or SAS activity indicator, active low.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A68

AC Coupling capacitor

PCIE_TX0-

A69

AC Coupling capacitor

B68

PCIE_RX0-

B69

A64

AC Coupling capacitor

PCIE_TX1-

A65

AC Coupling capacitor

B64

PCIE_RX1-

B65

A61

AC Coupling capacitor

PCIE_TX2-

A62

AC Coupling capacitor

B61

PCIE_RX2-

B62

A58

PCIE_TX3-

A59

B58

PCIE_RX3-

B59

A55

PCIE_TX4-

A56

B55

PCIE_RX4-

B56

A52

PCIE_TX5-

A53

B52

PCIE_RX5-

B53

D19

PCIE_TX6-

D20

C19

PCIE_RX6-

C20

D22

PCIE_TX7-

D23

C22

PCIE_RX7-

C23

PCIE0

A88

PCIE0_CK_REF-

A89

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

D52

PEG_TX0-

D53

C52

PEG_RX0-

C53

D55

PEG_TX1-

D56

C55

PEG_RX1-

C56

D58

PEG_TX2-

D59

C58

PEG_RX2-

C59

D61

PEG_TX3-

D62

C61

PEG_RX3-

C62

D65

PEG_TX4-

D66

C65

PEG_RX4-

C66

D68

PEG_TX5-

D69

C68

PEG_RX5-

C69

D71

PEG_TX6-

D72

C71

PEG_RX6-

C72

D74

PEG_TX7-

D75

C74

PEG_RX7-

C75

D78

PEG_TX8-

D79

C78

PEG_RX8-

C79

D81

PEG_TX9-

D82

C81

PEG_RX9-

C82

D85

PEG_TX10-

D86

C85

PEG_RX10-

C86

D88

PEG_TX11-

D89

C88

PEG_RX11-

C89

D91

PEG_TX12-

D92

C91

PEG_RX12-

C92

D94

PEG_TX13-

D95

C94

PEG_RX13-

C95

D98

PEG_TX14-

D99

C98

PEG_RX14-

C99

D101

PEG_TX15-

D102

C101

PEG_RX15-

C102

PEG_LANE_RV#

D54

I CMOS

3.3V / 3.3V

PU 10K to 3.3V

PCI Express Graphics lane reversal input strap. Pull low on the Carrier

board to reverse lane order.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

EXCD0_CPPE#

A49

EXCD1_CPPE#

B48

EXCD0_PERST#

A48

EXCD1_PERST#

B47

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

DDI/SD

D26

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR0-/SDVO1_RED-

D27

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D29

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR1-/SDVO1_GRN-

D30

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D32

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR2-/SDVO1_BLU-

D33

Connect AC Coupling Capacitors 0.1uF to Device

DDI/S

D36

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR3-/SDVO1_CK-

D37

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

C25

DDI1_PAIR4-/SDVO1_INT-

C26

DDI/SDVO1_

C29

DDI1_PAIR5-/SDVO1_TVCLKIN-

C30

DDI/SDVO1_F

C15

DDI1_PAIR6-/SDVO1_FLDSTALL-

C16

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

DDI1_HPD

C24

I CMOS

3.3V / 3.3V

PD 100K to GND

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI1_DDC_AUX_SEL

D34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI1_CTRL and DDI1_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm
resistor to configure the DDI[n]_AUX pair as the DDC channel.

Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

D39

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR0-

D40

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D42

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR1-

D43

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D46

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR2-

D47

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D49

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR3-

D50

Connect AC Coupling Capacitors 0.1uF to Device

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high

DDI2_HPD

D44

I CMOS

3.3V / 3.3V

PD 100K to GND

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI2_DDC_AUX_SEL

C34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI2_CTRL and DDI2_CTRLDATA_AUX-.

DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm
resistor to configure the DDI[n]_AUX pair as the DDC channel.
Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

C39

DDI3_PAIR0-

C40

DDI

C42

DDI3_PAIR1-

C43

DDI

C46

DDI3_PAIR2-

C47

DDI

C49

DDI3_PAIR3-

C50

I/O PCIE

AC coupled on Module

DP AUX+ function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

DP AUX- function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high

DDI3_HPD

C44

I CMOS

3.3V / 3.3V

DDI Hot-Plug Detect

DDI3_DDC_AUX_SEL

C38

I CMOS

3.3V / 3.3V

Selects the function of DDI3_CTRL and DDI3_CTRLDATA_AUX-.
DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.
Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

USB0+

A46

USB0-

A45

USB1+

B46

USB1-

B45

USB2+

A43

USB2-

A42

USB3+

B43

USB3-

B42

USB4+

A40

USB4-

A39

USB5+

B40

USB5-

B39

USB6+

A37

USB6-

A36

USB7+

B37

USB7-

B36

USB_0_1_OC#

B44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_2_3_OC#

A44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 2 and 3. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_4_5_OC#

B38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 4 and 5. A pull-up for this line

shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_6_7_OC#

A38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 6 and 7. A pull-up for this line

shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

AC Coupling capacitor

USB_SSTX0-

AC Coupling capacitor

USB_SSRX0-

AC Coupling capacitor

USB_SSTX1-

AC Coupling capacitor

USB_SSRX1-

D10

AC Coupling capacitor

USB_SSTX2-

AC Coupling capacitor

C10

USB_SSRX2-

D13

AC Coupling capacitor

USB_SSTX3-

D12

AC Coupling capacitor

C13

USB_SSRX3-

C12

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A71

LVDS_A0-

A72

A73

LVDS_A1-

A74

A75

LVDS_A2-

A76

A78

LVDS_A3-

A79

A81

LVDS_A_CK-

A82

B71

LVDS_B0-

B72

B73

LVDS_B1-

B74

B75

LVDS_B2-

B76

B77

LVDS_B3-

B78

B81

LVDS_B_CK-

B82

LVDS_VDD_EN

A77

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel power circuit

LVDS panel power enable

LVDS_BKLT_EN

B79

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel backlight power circuit.

LVDS panel backlight enable

LVDS_BKLT_CTRL

B83

O CMOS

3.3V / 3.3V

Connect to brightness control of LVDS panel backlight power circuit.

LVDS panel backlight brightness control

LVDS_I2C_CK

A83

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC clock of LVDS panel

I2C clock output for LVDS display use

LVDS_I2C_DAT

A84

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC data of LVDS panel

I2C data line for LVDS display use

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

O CMOS

3.3V / 3.3V

LPC frame indicates the start of an LPC cycle

LPC_DRQ0#

LPC_DRQ1#

LPC_SERIRQ

A50

I/O CMOS

3.3V / 3.3V

PU 1K to 3.3V

LPC serial interrupt

LPC_CLK

B10

O CMOS

3.3V / 3.3V

LPC clock output - 24MHz nominal

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

SPI_CS#

B97

O CMOS

3.3V Suspend/3.3V

Connect to Carrier Board SPI Device CS# pin

Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1

SPI_MISO

A92

I CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SO pin

Data in to Module from Carrier SPI

SPI_MOSI

A95

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SI pin

Data out from Module to Carrier SPI

SPI_CLK

A94

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SCK pin

Clock from Module to Carrier SPI

SPI_POWER

A91

3.3V Suspend/3.3V

Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier

BIOS_DIS0#

A34

PU 10K to 3.3V

BIOS_DIS1#

B88

PU 10K to 3.3V

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

VGA_RED

B89

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Red for monitor. Analog output

VGA_GRN

B91

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Green for monitor. Analog output

VGA_BLU

B92

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Blue for monitor. Analog output

VGA_HSYNC

B93

O CMOS

3.3V / 3.3V

Connect to VGA connector with a3.3V Buffer IC to isolate PCH & Display Device

Horizontal sync output to VGA monitor

VGA_VSYNC

B94

O CMOS

3.3V / 3.3V

Connect to VGA connector with a 33V Buffer IC to isolate PCH & Display Device

Vertical sync output to VGA monitor

VGA_I2C_CK

B95

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC clock line (I2C port dedicated to identify VGA monitor capabilities)

VGA_I2C_DAT

B96

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC data line.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

SER0_TX

A98

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 0 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER0_RX

A99

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 0 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_TX

A101

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 1 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_RX

A102

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 1 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

SPKR

B32

O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.

WDT

B27

O CMOS

3.3V / 3.3V

PD 100K to GND

Output indicating that a watchdog time-out event has occurred.

FAN_PWNOUT

B101

O OD CMOS

3.3V / 3.3V

Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

FAN_TACHIN

B102

I OD CMOS

3.3V / 3.3V

PU 47K to 3V3

Fan tachometer input for a fan with a two pulse output.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

TPM_PP

A96

I CMOS

3.3V / 3.3V

Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. This signal is used to indicate
Physical Presence to the TPM.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

PWRBTN#

B12

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU_EC

PU 4.7K to 3V3_SB

A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.

SYS_RESET#

B49

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3SB

NC PU 4.7K to 3V3_SB

Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.

CB_RESET#

B50

O CMOS

3.3V Suspend/3.3V

Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum

specification, a watchdog timeout, or may be initiated by the Module
software.

PWR_OK

B24

I CMOS

3.3V / 3.3V

PU 10K to 3V3

Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.

SUS_STAT#

B18

O CMOS

3.3V Suspend/3.3V

PU 1K to 3V3SB

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3#

A15

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.

SUS_S4#

A18

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

A24

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Indicates system is in Soft Off state.

WAKE0#

B66

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3SB

PCI Express wake up signal.

WAKE1#

B67

I CMOS

3.3V Suspend/3.3V

General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.

BATLOW#

A27

I CMOS

3.3V Suspend/ 3.3V

PU 10K to 3V3SB

Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.

LID#

A103

I OD CMOS

3.3V Suspend/12V

PU 47K to 3V3_DU_EC

LID switch. Low active signal used by the ACPI operating system for a LID switch.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SLEEP#

B103

I OD CMOS

3.3V Suspend/12V

PU 4.7K to 3V3_DU

Sleep button. Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

THRM#

B35

I CMOS

3.3V / 3.3V

PU 1K to 3V3

Input from off-Module temp sensor indicating an over-temp situation.

THRMTRIP#

A35

O CMOS

3.3V / 3.3V

PU 1K to 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

SMB_CK

B13

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional clock line.

SMB_DAT

B14

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional data line.

SMB_ALERT#

B15

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU_EC

System Management Bus Alert – active low input can be used to
generate an SMI# (System Management Interrupt) or to wake the system.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

GPO0

A93

GPO1

B54

GPO2

B57

GPO3

B63

GPI0

A54

PU 47K to 3.3V

GPI1

A63

PU 47K to 3.3V

GPI2

A67

PU 47K to 3.3V

GPI3

A85

PU 47K to 3.3V

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

VCC_12V

A104~A109
B104~B109
C104~C109
D104~D109

Power

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

VCC_5V_SBY

B84~B87

Power

Standby power input: +5.0V nominal. If VCC5_SBY is used, all
available VCC_5V_SBY pins on the connector(s) shall be used. Only
used for standby and suspend functions. May be left unconnected if
these functions are not used in the system design.

VCC_RTC

A47

Power

Real-time clock circuit-power input. Nom3.0V.

GND

A1, A11, A21, A31,
A41, A51, A57, A60,
A66, A70, A80, A90,
A100, A110, B1,
B11, B21 ,B31, B41,
B51, B60, B70, B80,
B90, B100, B110,
C1, C2, C5, C8, C11,
C14, C21, C31, C41,
C51, C60, C70, C73,
C76, C80, C84, C87,
C90, C93, C96,
C100, C103, C110,
D1, D2, D5, D8,
D11, D14, D21,
D31, D51, D60,
D67, D70, D73,
D76, D80, D84,
D87, D90, D93,
D96, D100, D103,
D110

Power

Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier
Board GND plane.

Connect to LPC device

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Pin Types
I Input to the Module

O Output from the Module
I/O Bi-directional input / output signal

OD Open drain output

AC coupled off Module

Serial Digital Video Field Stall input differential pair.

O PCIE

AC coupled off Module

DDI 1 Pair 3 differential pairs/Serial Digital Video B clock output differential pair.

I PCIE

AC coupled off Module

Serial Digital Video TVOUT synchronization clock input differential pair.

AC coupled off Module

Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options of BIOS disable signals.

LVDS Channel B differential clock

LPC Signals and Descriptions

O PCIE

AC coupled off Module

DDI 3 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 3 differential pairs

DDI 3 Pair 2 differential pairs

O PCIE

DDI 3 Pair 1 differential pairs

DDI3_CTRL

C36

DDI3_CTRLCLK_AUX-

C37

O PCIE

AC coupled off Module

DDI 2 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 3 Pair 3 differential pairs

AC coupled off Module

DDI Signals and Descriptions

O PCIE

AC coupled off Module

DDI 1 Pair 0 differential pairs/Serial Digital Video B red output differential pair

I PCIE

3.3V / 3.3V

LPC serial DMA request

SPI Signals and Descriptions

O PCIE

AC coupled off Module

DDI 2 Pair 2 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 1 differential pairs

O PCIE

AC coupled off Module

DDI2_CTRL

C32

DDI2_CTRLCLK_AUX-

C33

DDI1_CTRL/SDVO1_CTRLCLK D15

DDI1_CTRLCLK_AUX-/SDVO1_CTRLDATA D16

AC coupled off Module

DDI 1 Pair 2 differential pairs/Serial Digital Video B blue output differential pair

O PCIE

AC coupled off Module

DDI 1 Pair 1 differential pairs/Serial Digital Video B green output differential pair

Power and GND Signals and Descriptions

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

I/O CMOS

3.3V / 3.3V

I CMOS

3.3V / 3.3V

General purpose input pins.

Pulled high internally on the Module.

Power and System Management Signals and Descriptions

GPIO Signals and Descriptions

O CMOS

Serial Digital Video B interrupt input differential pair.

General purpose output pins.

Upon a hardware reset, these outputs should be low.

VGA Signals and Descriptions

3.3V / 3.3V

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

LPC multiplexed address, command and data bus

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel B differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,
LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential clock

O LVDS

LVDS

Connect to LVDS connector

Serial Interface Signals and Descriptions

Miscellaneous Signals and Descriptions

I CMOS

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 7

LVDS Signals and Descriptions

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,

LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer
on-board

O LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 2

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 1

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 6

O CMOS

3.3V /3.3V

PCI ExpressCard: reset, active low, one per card

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 4

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 3

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 5

USB Signals and Descriptions

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 14

PCI Express Graphics receive differential pairs 12

ExpressCard Signals and Descriptions

I CMOS

3.3V /3.3V

PCI ExpressCard: PCI Express capable card request, active low, one per

card

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 14

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 15

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 15

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 11

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 11

PCI Express Graphics receive differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 8

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 8

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 5

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 6

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 5

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 7

AC coupled on Module

PCI Express Graphics transmit differential pairs 7

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 6

PCI Express Graphics transmit differential pairs 4

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 3

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 2

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 3

PCI Express Graphics receive differential pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

I PCIE

PCI Express Graphics transmit differential pairs 2

PEG Signals and Descriptions

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 0

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 1

AC coupled off Module

PCI Express Graphics receive differential pairs 1

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Receive Pairs 7

O PCIE

PCIE

Connect to PCIE device,

PCIe CLK Buffer

or slot

Reference clock output for all PCI Express and PCI Express Graphics
lanes.

PCI Express Differential Receive Pairs 6

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 7

PCI Express Differential Transmit Pairs 4

PCI Express Differential Receive Pairs 2

PCI Express Differential Transmit Pairs 6

PCI Express Differential Transmit Pairs 3

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 5

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 5

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

AC coupled on Module

PCI Express Differential Transmit Pairs 1

PCI Express Differential Receive Pairs 1

PCI Express Differential Receive Pairs 3

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 0

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 2

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 0

I PCIE

AC coupled off Module

O PCIE

AC97/HDA Signals and Descriptions

Serial TDM data inputs from up to 2 CODECs.

Gigabit Ethernet Signals and Descriptions

PCI Express Lanes Signals and Descriptions

Serial ATA or SAS Channel 0 transmit differential pair.

Connect to SATA0 Conn RX pin

Serial ATA or SAS Channel 0 receive differential pair.

Connect to SATA1 Conn TX pin

Connect to SATA2 Conn TX pin

Serial ATA or SAS Channel 3 transmit differential pair.

Serial ATA or SAS Channel 3 receive differential pair.

Connect to SATA2 Conn RX pin

Serial ATA or SAS Channel 2 receive differential pair.

Serial ATA or SAS Channel 2 transmit differential pair.

Connect to SATA1 Conn RX pin

Serial ATA or SAS Channel 1 receive differential pair.

SATA Signals and Descriptions

Connect to SATA0 Conn TX pin

Serial ATA or SAS Channel 1 transmit differential pair.

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

Ref

Line

Bios

Entry

SPI

Descriptor

Carrier

SPI_CS#

Chipset

SPI CS0#

Destination

Chipset

SPI CS1#

Destination

BIOS

DIS0#

BIOS

DIS1#

Module

SPI0/SPI1

SPI1

(Default)

SPI0

High

Carrier

Carrier

(Default)

Module

(Default)

Module

Module

(Default)

Module

Carrier FWH

SPI0/SPI1

(Default)

SPI0/SPI1

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

AC/HAD_RST#

A30

O CMOS

3.3V Suspend/3.3V

Connect to CODEC pin 11 RESET#

Reset output to CODEC, active low.

AC/HDA_SYNC

A29

O CMOS

3.3V/3.3V

Connect to CODEC pin 10 SYNC

Sample-synchronization signal to the CODEC(s).

AC/HDA_BITCLK

A32

I/O CMOS

3.3V/3.3V

Connect to CODEC pin 6 BIT_CLK

Serial data clock generated by the external CODEC(s).

AC/HDA_SDOUT

A33

O CMOS

3.3V/3.3V

Connect to CODEC pin 5 SDATA_OUT

Serial TDM data output to the CODEC.

AC/HDA_SDIN2

B28

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN1

B29

I/O CMOS

3.3V Suspend/3.3V

AC/HDA_SDIN0

B30

I/O CMOS

3.3V Suspend/3.3V

Connect 33

Ω

in series to CODEC0 pin 8 SDATA_IN

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A13

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI0+/-

Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec

modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-

MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

GBE0_MDI0-

A12

I/O Analog

3.3V max Suspend

A10

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI1+/-

GBE0_MDI1-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI2+/-

GBE0_MDI2-

I/O Analog

3.3V max Suspend

I/O Analog

3.3V max Suspend

Connect to Magnetics Module MDI3+/-

GBE0_MDI3-

I/O Analog

3.3V max Suspend

GBE0_ACT#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Gigabit Ethernet Controller 0 activity indicator, active low.

GBE0_LINK#

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 link indicator, active low.

GBE0_LINK100#

OD CMOS

3.3V Suspend/3.3V

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

GBE0_LINK100#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

GBE0_LINK1000#

OD CMOS

3.3V Suspend/3.3V

Connect to LED and

recommend

current limit resistor 150

to 3.3VSB

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA0_TX-

A17

O SATA

AC coupled on Module

AC Coupling capacitor

A19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA0_RX-

A20

I SATA

AC coupled on Module

AC Coupling capacitor

B16

O SATA

AC coupled on Module

AC Coupling capacitor

SATA1_TX-

B17

O SATA

AC coupled on Module

AC Coupling capacitor

B19

I SATA

AC coupled on Module

AC Coupling capacitor

SATA1_RX-

B20

I SATA

AC coupled on Module

AC Coupling capacitor

A22

O SATA

AC coupled on Module

SATA2_TX-

A23

O SATA

AC coupled on Module

A25

I SATA

AC coupled on Module

SATA2_RX-

A26

I SATA

AC coupled on Module

B22

O SATA

AC coupled on Module

SATA3_TX-

B23

O SATA

AC coupled on Module

B25

I SATA

AC coupled on Module

SATA3_RX-

B26

I SATA

AC coupled on Module

ATA_ACT#

A28

I/O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Connect to LED and

recommend

current limit resistor 220

Ω

to 3.3V

ATA (parallel and serial) or SAS activity indicator, active low.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A68

AC Coupling capacitor

PCIE_TX0-

A69

AC Coupling capacitor

B68

PCIE_RX0-

B69

A64

AC Coupling capacitor

PCIE_TX1-

A65

AC Coupling capacitor

B64

PCIE_RX1-

B65

A61

AC Coupling capacitor

PCIE_TX2-

A62

AC Coupling capacitor

B61

PCIE_RX2-

B62

A58

PCIE_TX3-

A59

B58

PCIE_RX3-

B59

A55

PCIE_TX4-

A56

B55

PCIE_RX4-

B56

A52

PCIE_TX5-

A53

B52

PCIE_RX5-

B53

D19

PCIE_TX6-

D20

C19

PCIE_RX6-

C20

D22

PCIE_TX7-

D23

C22

PCIE_RX7-

C23

PCIE0

A88

PCIE0_CK_REF-

A89

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

D52

PEG_TX0-

D53

C52

PEG_RX0-

C53

D55

PEG_TX1-

D56

C55

PEG_RX1-

C56

D58

PEG_TX2-

D59

C58

PEG_RX2-

C59

D61

PEG_TX3-

D62

C61

PEG_RX3-

C62

D65

PEG_TX4-

D66

C65

PEG_RX4-

C66

D68

PEG_TX5-

D69

C68

PEG_RX5-

C69

D71

PEG_TX6-

D72

C71

PEG_RX6-

C72

D74

PEG_TX7-

D75

C74

PEG_RX7-

C75

D78

PEG_TX8-

D79

C78

PEG_RX8-

C79

D81

PEG_TX9-

D82

C81

PEG_RX9-

C82

D85

PEG_TX10-

D86

C85

PEG_RX10-

C86

D88

PEG_TX11-

D89

C88

PEG_RX11-

C89

D91

PEG_TX12-

D92

C91

PEG_RX12-

C92

D94

PEG_TX13-

D95

C94

PEG_RX13-

C95

D98

PEG_TX14-

D99

C98

PEG_RX14-

C99

D101

PEG_TX15-

D102

C101

PEG_RX15-

C102

PEG_LANE_RV#

D54

I CMOS

3.3V / 3.3V

PU 10K to 3.3V

PCI Express Graphics lane reversal input strap. Pull low on the Carrier
board to reverse lane order.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

EXCD0_CPPE#

A49

EXCD1_CPPE#

B48

EXCD0_PERST#

A48

EXCD1_PERST#

B47

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

DDI/SD

D26

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR0-/SDVO1_RED-

D27

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D29

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR1-/SDVO1_GRN-

D30

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

D32

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR2-/SDVO1_BLU-

D33

Connect AC Coupling Capacitors 0.1uF to Device

DDI/S

D36

Connect AC Coupling Capacitors 0.1uF to Device

DDI1_PAIR3-/SDVO1_CK-

D37

Connect AC Coupling Capacitors 0.1uF to Device

DDI/SD

C25

DDI1_PAIR4-/SDVO1_INT-

C26

DDI/SDVO1_

C29

DDI1_PAIR5-/SDVO1_TVCLKIN-

C30

DDI/SDVO1_F

C15

DDI1_PAIR6-/SDVO1_FLDSTALL-

C16

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI1_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

DDI1_HPD

C24

I CMOS

3.3V / 3.3V

PD 100K to GND

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI1_DDC_AUX_SEL

D34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI1_CTRL and DDI1_CTRLDATA_AUX-.
DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.
Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

D39

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR0-

D40

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D42

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR1-

D43

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D46

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR2-

D47

Connect AC Coupling Capacitors 0.1uF to Device

DDI

D49

Connect AC Coupling Capacitors 0.1uF to Device

DDI2_PAIR3-

D50

Connect AC Coupling Capacitors 0.1uF to Device

I/O PCIE

AC coupled on Module

PD 100K to GND

(S/W IC between Rpu/PCH)

Connect to DP AUX+

DP AUX+ function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V, PD 100K to GND

(S/W IC between Rpu/Rpd

resistor)

Connect to HDMI/DVI I2C CTRLCLK

HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module PU 100K to 3.3V

(S/W IC between Rpu/PCH)

Connect to DP AUX-

DP AUX- function if DDI2_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V/PU 100K to 3.3V

(S/W IC between 4.7K/100K

resistor)

Connect to HDMI/DVI I2C CTRLDATA

HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high

DDI2_HPD

D44

I CMOS

3.3V / 3.3V

PD 100K to GND

PD 1M and Connect to device Hot Plug Detect

DDI Hot-Plug Detect

DDI2_DDC_AUX_SEL

C34

I CMOS

3.3V / 3.3V

PD 1M to GND

PU 100K to 3.3V for DDC(HDMI/DVI)

Selects the function of DDI2_CTRL and DDI2_CTRLDATA_AUX-.
DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.
Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

DDI

C39

DDI3_PAIR0-

C40

DDI

C42

DDI3_PAIR1-

C43

DDI

C46

DDI3_PAIR2-

C47

DDI

C49

DDI3_PAIR3-

C50

I/O PCIE

AC coupled on Module

DP AUX+ function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

I/O PCIE

AC coupled on Module

DP AUX- function if DDI3_DDC_AUX_SEL is no connect

I/O OD CMOS

3.3V / 3.3V

HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high

DDI3_HPD

C44

I CMOS

3.3V / 3.3V

DDI Hot-Plug Detect

DDI3_DDC_AUX_SEL

C38

I CMOS

3.3V / 3.3V

Selects the function of DDI3_CTRL and DDI3_CTRLDATA_AUX-.
DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm

resistor to configure the DDI[n]_AUX pair as the DDC channel.
Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

USB0+

A46

USB0-

A45

USB1+

B46

USB1-

B45

USB2+

A43

USB2-

A42

USB3+

B43

USB3-

B42

USB4+

A40

USB4-

A39

USB5+

B40

USB5-

B39

USB6+

A37

USB6-

A36

USB7+

B37

USB7-

B36

USB_0_1_OC#

B44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_2_3_OC#

A44

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 2 and 3. A pull-up for this line

shall be present on the Module. An open drain driver from a USB

current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_4_5_OC#

B38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 4 and 5. A pull-up for this line

shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

USB_6_7_OC#

A38

I CMOS

3.3V Suspend/3.3V

PU 10k to 3V3SB

Connect to Overcurrent of USB Power Switch

USB over-current sense, USB channels 6 and 7. A pull-up for this line

shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.

AC Coupling capacitor

USB_SSTX0-

AC Coupling capacitor

USB_SSRX0-

AC Coupling capacitor

USB_SSTX1-

AC Coupling capacitor

USB_SSRX1-

D10

AC Coupling capacitor

USB_SSTX2-

AC Coupling capacitor

C10

USB_SSRX2-

D13

AC Coupling capacitor

USB_SSTX3-

D12

AC Coupling capacitor

C13

USB_SSRX3-

C12

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

A71

LVDS_A0-

A72

A73

LVDS_A1-

A74

A75

LVDS_A2-

A76

A78

LVDS_A3-

A79

A81

LVDS_A_CK-

A82

B71

LVDS_B0-

B72

B73

LVDS_B1-

B74

B75

LVDS_B2-

B76

B77

LVDS_B3-

B78

B81

LVDS_B_CK-

B82

LVDS_VDD_EN

A77

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel power circuit

LVDS panel power enable

LVDS_BKLT_EN

B79

O CMOS

3.3V / 3.3V

Connect to enable control of LVDS panel backlight power circuit.

LVDS panel backlight enable

LVDS_BKLT_CTRL

B83

O CMOS

3.3V / 3.3V

Connect to brightness control of LVDS panel backlight power circuit.

LVDS panel backlight brightness control

LVDS_I2C_CK

A83

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC clock of LVDS panel

I2C clock output for LVDS display use

LVDS_I2C_DAT

A84

I/O OD CMOS

3.3V / 3.3V

PU 4.7K to 3.3V

Connect to DDC data of LVDS panel

I2C data line for LVDS display use

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

O CMOS

3.3V / 3.3V

LPC frame indicates the start of an LPC cycle

LPC_DRQ0#

LPC_DRQ1#

LPC_SERIRQ

A50

I/O CMOS

3.3V / 3.3V

PU 1K to 3.3V

LPC serial interrupt

LPC_CLK

B10

O CMOS

3.3V / 3.3V

LPC clock output - 24MHz nominal

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

SPI_CS#

B97

O CMOS

3.3V Suspend/3.3V

Connect to Carrier Board SPI Device CS# pin

Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1

SPI_MISO

A92

I CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SO pin

Data in to Module from Carrier SPI

SPI_MOSI

A95

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SI pin

Data out from Module to Carrier SPI

SPI_CLK

A94

O CMOS

3.3V Suspend/3.3V

Connect a series resistor 33

to Carrier Board SPI Device SCK pin

Clock from Module to Carrier SPI

SPI_POWER

A91

3.3V Suspend/3.3V

BIOS_DIS0#

A34

PU 10K to 3.3V

BIOS_DIS1#

B88

PU 10K to 3.3V

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

VGA_RED

B89

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Red for monitor. Analog output

VGA_GRN

B91

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Green for monitor. Analog output

VGA_BLU

B92

O Analog

Analog

PD 150 to GND

PD 150R,connect to VGA connector with EMI filter & ESD protect component.

Blue for monitor. Analog output

VGA_HSYNC

B93

O CMOS

3.3V / 3.3V

Connect to VGA connector with a3.3V Buffer IC to isolate PCH & Display Device

Horizontal sync output to VGA monitor

VGA_VSYNC

B94

O CMOS

3.3V / 3.3V

Connect to VGA connector with a 33V Buffer IC to isolate PCH & Display Device

Vertical sync output to VGA monitor

VGA_I2C_CK

B95

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC clock line (I2C port dedicated to identify VGA monitor capabilities)

VGA_I2C_DAT

B96

I/O OD CMOS

3.3V / 3.3V

PU 2.2K to 3.3V

Connect to VGA connector with a 3.3V to 5V Level shift circuit.

DDC data line.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

SER0_TX

A98

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 0 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER0_RX

A99

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 0 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_TX

A101

O CMOS

3.3V/5V

PD 4.7K to GND

General purpose serial port 1 transmitter

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SER1_RX

A102

I CMOS

3.3V/5V

PU 10K to 3.3V

General purpose serial port 1 receiver

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

SPKR

B32

O CMOS

3.3V / 3.3V

PU 10K to 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.

WDT

B27

O CMOS

3.3V / 3.3V

PD 100K to GND

Output indicating that a watchdog time-out event has occurred.

FAN_PWNOUT

B101

O OD CMOS

3.3V / 3.3V

Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

FAN_TACHIN

B102

I OD CMOS

3.3V / 3.3V

PU 47K to 3V3

Fan tachometer input for a fan with a two pulse output.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

TPM_PP

A96

I CMOS

3.3V / 3.3V

Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. This signal is used to indicate
Physical Presence to the TPM.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

PWRBTN#

B12

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU_EC

PU 4.7K to 3V3_SB

A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.

SYS_RESET#

B49

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3SB

NC PU 4.7K to 3V3_SB

CB_RESET#

B50

O CMOS

3.3V Suspend/3.3V

Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.

PWR_OK

B24

I CMOS

3.3V / 3.3V

PU 10K to 3V3

SUS_STAT#

B18

O CMOS

3.3V Suspend/3.3V

PU 1K to 3V3SB

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3#

A15

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.

SUS_S4#

A18

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

A24

O CMOS

3.3V Suspend/3.3V

PD 100K to GND

Indicates system is in Soft Off state.

WAKE0#

B66

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3SB

PCI Express wake up signal.

WAKE1#

B67

I CMOS

3.3V Suspend/3.3V

General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.

BATLOW#

A27

I CMOS

3.3V Suspend/ 3.3V

PU 10K to 3V3SB

Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.

LID#

A103

I OD CMOS

3.3V Suspend/12V

PU 47K to 3V3_DU_EC

LID switch. Low active signal used by the ACPI operating system for a LID switch.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

SLEEP#

B103

I OD CMOS

3.3V Suspend/12V

PU 4.7K to 3V3_DU

Sleep button. Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.

(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)

THRM#

B35

I CMOS

3.3V / 3.3V

PU 1K to 3V3

Input from off-Module temp sensor indicating an over-temp situation.

THRMTRIP#

A35

O CMOS

3.3V / 3.3V

PU 1K to 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

SMB_CK

B13

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional clock line.

SMB_DAT

B14

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3V3_DU_EC

System Management Bus bidirectional data line.

SMB_ALERT#

B15

I CMOS

3.3V Suspend/3.3V

PU 10K to 3V3_DU_EC

System Management Bus Alert – active low input can be used to
generate an SMI# (System Management Interrupt) or to wake the system.

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

GPO0

A93

GPO1

B54

GPO2

B57

GPO3

B63

GPI0

A54

PU 47K to 3.3V

GPI1

A63

PU 47K to 3.3V

GPI2

A67

PU 47K to 3.3V

GPI3

A85

PU 47K to 3.3V

Signal

Pin#

Module Pin Type

Pwr Rail /Tolerance

BW968

Carrier Board

Description

VCC_12V

A104~A109
B104~B109
C104~C109
D104~D109

Power

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

VCC_5V_SBY

B84~B87

Power

VCC_RTC

A47

Power

Real-time clock circuit-power input. Nom3.0V.

GND

D11, D14, D21,
D31, D51, D60,
D67, D70, D73,
D76, D80, D84,
D87, D90, D93,
D96, D100, D103,
D110

Power

Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier
Board GND plane.

Connect to LPC device

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Pin Types
I Input to the Module

O Output from the Module
I/O Bi-directional input / output signal

OD Open drain output

AC coupled off Module

Serial Digital Video Field Stall input differential pair.

O PCIE

AC coupled off Module

DDI 1 Pair 3 differential pairs/Serial Digital Video B clock output differential pair.

I PCIE

AC coupled off Module

Serial Digital Video TVOUT synchronization clock input differential pair.

AC coupled off Module

LVDS Channel B differential clock

LPC Signals and Descriptions

O PCIE

AC coupled off Module

DDI 3 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 3 differential pairs

DDI 3 Pair 2 differential pairs

O PCIE

DDI 3 Pair 1 differential pairs

DDI3_CTRL

C36

DDI3_CTRLCLK_AUX-

C37

O PCIE

AC coupled off Module

DDI 2 Pair 0 differential pairs

O PCIE

AC coupled off Module

DDI 3 Pair 3 differential pairs

AC coupled off Module

DDI Signals and Descriptions

O PCIE

AC coupled off Module

DDI 1 Pair 0 differential pairs/Serial Digital Video B red output differential pair

I PCIE

3.3V / 3.3V

LPC serial DMA request

SPI Signals and Descriptions

O PCIE

AC coupled off Module

DDI 2 Pair 2 differential pairs

O PCIE

AC coupled off Module

DDI 2 Pair 1 differential pairs

O PCIE

AC coupled off Module

DDI2_CTRL

C32

DDI2_CTRLCLK_AUX-

C33

DDI1_CTRL/SDVO1_CTRLCLK D15

DDI1_CTRLCLK_AUX-/SDVO1_CTRLDATA D16

AC coupled off Module

DDI 1 Pair 2 differential pairs/Serial Digital Video B blue output differential pair

O PCIE

AC coupled off Module

DDI 1 Pair 1 differential pairs/Serial Digital Video B green output differential pair

Power and GND Signals and Descriptions

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

I/O CMOS

3.3V / 3.3V

I CMOS

3.3V / 3.3V

General purpose input pins.

Pulled high internally on the Module.

Power and System Management Signals and Descriptions

GPIO Signals and Descriptions

O CMOS

Serial Digital Video B interrupt input differential pair.

General purpose output pins.

Upon a hardware reset, these outputs should be low.

VGA Signals and Descriptions

3.3V / 3.3V

O LVDS

LVDS

Connect to LVDS connector

O LVDS

LVDS

LPC multiplexed address, command and data bus

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel B differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,
LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential clock

O LVDS

LVDS

Connect to LVDS connector

Serial Interface Signals and Descriptions

Miscellaneous Signals and Descriptions

I CMOS

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 7

LVDS Signals and Descriptions

O LVDS

LVDS

Connect to LVDS connector

LVDS Channel A differential pairs

Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LV/-,
LV/-) shall have 100

Ω

terminations across the pairs at the destination. These

terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer

on-board

O LVDS

Connect to LVDS connector

O LVDS

LVDS

Connect to LVDS connector

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

O PCIE

AC coupled on Module

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional transmit signal differential pairs for the SuperSpeed USB data path.

I PCIE

AC coupled off Modul

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

Additional receive signal differential pairs for the SuperSpeed USB data path.

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 2

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 1

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 6

O CMOS

3.3V /3.3V

PCI ExpressCard: reset, active low, one per card

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 4

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 3

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 5

USB Signals and Descriptions

I/O USB

3.3V Suspend/3.3V

Connect 90

Ω

@100MHz Common Choke in series and ESD suppressors to GND to USB

connector

USB differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 14

PCI Express Graphics receive differential pairs 12

ExpressCard Signals and Descriptions

I CMOS

3.3V /3.3V

PCI ExpressCard: PCI Express capable card request, active low, one per

card

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 14

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 15

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 15

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 13

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 12

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 11

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 11

PCI Express Graphics receive differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 8

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 10

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 9

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 8

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 5

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 6

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 5

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 7

AC coupled on Module

PCI Express Graphics transmit differential pairs 7

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 6

PCI Express Graphics transmit differential pairs 4

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 3

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 2

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 3

PCI Express Graphics receive differential pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

I PCIE

PCI Express Graphics transmit differential pairs 2

PEG Signals and Descriptions

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 0

I PCIE

AC coupled off Module

PCI Express Graphics receive differential pairs 0

O PCIE

AC coupled on Module

PCI Express Graphics transmit differential pairs 1

AC coupled off Module

PCI Express Graphics receive differential pairs 1

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Receive Pairs 7

O PCIE

PCIE

Connect to PCIE device,

PCIe CLK Buffer

or slot

Reference clock output for all PCI Express and PCI Express Graphics
lanes.

PCI Express Differential Receive Pairs 6

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 7

PCI Express Differential Transmit Pairs 4

PCI Express Differential Receive Pairs 2

PCI Express Differential Transmit Pairs 6

PCI Express Differential Transmit Pairs 3

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 5

I PCIE

AC coupled off Module

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 5

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 4

O PCIE

AC coupled on Module

O PCIE

AC coupled on Module

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

Connect to PCIE device or slot

Device

- Connect AC Coupling cap 0.1uF

Slot

- Connect to PCIE Conn pin

AC coupled on Module

PCI Express Differential Transmit Pairs 1

PCI Express Differential Receive Pairs 1

PCI Express Differential Receive Pairs 3

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 0

O PCIE

AC coupled on Module

PCI Express Differential Transmit Pairs 2

I PCIE

AC coupled off Module

I PCIE

AC coupled off Module

PCI Express Differential Receive Pairs 0

I PCIE

AC coupled off Module

O PCIE

AC97/HDA Signals and Descriptions

Serial TDM data inputs from up to 2 CODECs.

Gigabit Ethernet Signals and Descriptions

PCI Express Lanes Signals and Descriptions

Serial ATA or SAS Channel 0 transmit differential pair.

Connect to SATA0 Conn RX pin

Serial ATA or SAS Channel 0 receive differential pair.

Connect to SATA1 Conn TX pin

Connect to SATA2 Conn TX pin

Serial ATA or SAS Channel 3 transmit differential pair.

Serial ATA or SAS Channel 3 receive differential pair.

Connect to SATA2 Conn RX pin

Serial ATA or SAS Channel 2 receive differential pair.

Serial ATA or SAS Channel 2 transmit differential pair.

Connect to SATA1 Conn RX pin

Serial ATA or SAS Channel 1 receive differential pair.

SATA Signals and Descriptions

Connect to SATA0 Conn TX pin

Serial ATA or SAS Channel 1 transmit differential pair.

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

Ref

Line

Bios

Entry

SPI

Descriptor

Carrier

SPI_CS#

Chipset

SPI CS0#

Destination

Chipset

SPI CS1#

Destination

BIOS

DIS0#

BIOS

DIS1#

Module

SPI0/SPI1

SPI1

(Default)

SPI0

High

Carrier

Carrier

(Default)

Module

(Default)

Module

Module

(Default)

Module

Carrier FWH

SPI0/SPI1

(Default)

SPI0/SPI1

Содержание BW968

Страница 1: ...www dfi com Chapter 1 Introduction 1 BW968 COM Express Compact Module User s Manual A38100644...

Страница 2: ...M Express ModuleTM Base Specification http www picmg org FCC and DOC Statement on Class B This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Pa...

Страница 3: ...re Installation 10 Board Layout 10 Block Diagram 10 Mechanical Diagram 11 System Memory 12 Connectors 13 CPU Fan Connector 13 COM Express Connectors 13 COM Express Connectors 14 COM Express Connectors...

Страница 4: ...your system unit Static electrical discharge can damage computer components without causing any signs of physical damage You must take extra care in han dling them to ensure against electrostatic bui...

Страница 5: ...may differ in accordance with the sales region or models in which it was sold For more information about the standard package in your region please contact your dealer or sales representative Before U...

Страница 6: ...ansion Interface 3 x PCIe x1 Gen 2 1 x LPC 1 x I2 C 1 x SMBus 2 x Serial TX RX Audio Interface HD Audio Ethernet Controller 1 x Intel I211AT PCIe 10 100 1000Mbps I O USB 4 x USB 3 0 8 x USB 2 0 SATA 2...

Страница 7: ...nce and compat ibility needed for today s and tomorrow s business applications Supports 1 x VGA DDI 1 x LVDS eDP and 1 DDI interfaces for triple display outputs Serial ATA Serial ATA is a storage inte...

Страница 8: ...Basic Compact Mini 74 20 80 00 91 00 121 00 151 00 Common for all Form Factors Extended only Basic only Compact only Compact and Basic only Mini only COM Express Module Standards The figure below sho...

Страница 9: ...0 Ports 4 8 8 A B USB Client 0 1 0 A B USB 3 0 Ports NA NA A B LAN Port 0 1 1 1 A B Express Card Support 1 2 2 A B LPC Bus 1 1 1 A B SPI 1 2 1 A B SDIO muxed on GPIO 0 1 0 General Purpose I O 8 8 8 A...

Страница 10: ...2 1 x1 LPC Bus 8 bit DIO WDT I2 C Bus TPM 1 2 2 0 optional Serial Port 0 1 Fan PWM TACH_IN SLP LID TCA6408A Embedded Controller IT8518E DDR3L 1600MHz SODIMM Channel B DDI Port 1 HDA USB 2 0 4x USB 2 0...

Страница 11: ...Diagram BW968 Module with Heat Sink Side View of the Module with Heat Sink BW968 Module Top View Bottom View 16 00 0 30 3 50 3 00 1 40 7 00 94 00 95 00 4 00 91 00 83 00 8 00 87 00 12 50 78 75 87 25 88...

Страница 12: ...p and attaching it to a metal part of the system chassis If a wrist strap is unavailable establish and maintain contact with the system chassis throughout any procedures requiring ESD protection Impor...

Страница 13: ...nformation 3 1 Sense 12V Ground COM Express Connectors The COM Express connectors are used to interface the BW968 COM Express board to a carrier board Connect the COM Express connectors located on the...

Страница 14: ...12V A55 NA B55 NA A110 GND FIXED B110 GND FIXED C55 NA D55 NA C110 GND FIXED D110 GND FIXED Row C Row D Row A Row B Row C Row D Row A Row B A1 GND FIXED B1 GND FIXED A56 NA B56 NA C1 GND FIXED D1 GND...

Страница 15: ...ignal Pin Module Pin Type Pwr Rail Tolerance BW968 Carrier Board Description PEG_TX0 D52 NA PEG_TX0 D53 NA PEG_RX0 C52 NA PEG_RX0 C53 NA PEG_TX1 D55 NA PEG_TX1 D56 NA PEG_RX1 C55 NA PEG_RX1 C56 NA PEG...

Страница 16: ...NA Connect to PCIE device or slot Device Connect AC Coupling cap 0 1uF Slot Connect to PCIE Conn pin Connect to PCIE device or slot Device Connect AC Coupling cap 0 1uF Slot Connect to PCIE Conn pin...

Страница 17: ...l pair Serial ATA or SAS Channel 1 transmit differential pair SATA0_TX A17 O SATA AC coupled on Module AC Coupling capacitor SATA0_RX A19 I SATA AC coupled on Module AC Coupling capacitor SATA0_RX A20...

Страница 18: ...l this line high on the Carrier Board USB_4_5_OC B38 I CMOS 3 3V Suspend 3 3V PU 10k to 3V3SB Connect to Overcurrent of USB Power Switch USB over current sense USB channels 4 and 5 A pull up for this...

Страница 19: ...V 3 3V PU 1K to 3 3V LPC serial interrupt LPC_CLK B10 O CMOS 3 3V 3 3V LPC clock output 24MHz nominal Signal Pin Module Pin Type Pwr Rail Tolerance BW968 Carrier Board Description SPI_CS B97 O CMOS 3...

Страница 20: ...I CMOS 3 3V Suspend 3 3V PU 10K to 3V3SB NC PU 4 7K to 3V3_SB Reset button input Active low request for Module to reset and reboot May be falling edge sensitive For situations when SYS_RESET is not ab...

Страница 21: ...ipset and may result from a low SYS_RESET input a low PWR_OK input a VCC_12V power input that falls below the minimum specification a watchdog timeout or may be initiated by the Module software PWR_OK...

Страница 22: ...ignal used by the ACPI operating system to bring the system to sleep state or to wake it up again Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V THRM B35 I CMOS 3 3V 3 3V...

Страница 23: ...ons Heat Sink with Cooling Fan 1 denotes the location of the thermal pad paste designed to contact the corre sponding components that are on BW968 Top View of the Heat Sink Important Remove the plasti...

Страница 24: ...uide you on how to install BW968 onto the carrier board of your choice 2 Grasp BW968 by its edges and position it on top of the carrier board with the mounting holes of BW968 aligning with the standof...

Страница 25: ...tion 25 Chapter 3 4 Verify that BW968 is firmly seated in the COM Express connectors of the carrier board Carrier board BW968 5 Install a heat sink onto the BW968 with the carrier board The photo belo...

Страница 26: ...rd designed for COM Express Compact modules to debug and display signals and codes of COM Express modules COMe LINK1 Bottom view Top view COMe DEBUG Connector COM Express Connectors 2 Connect the COMe...

Страница 27: ...OMe LINK1 debug card onto the carrier board COMe LINK1 Carrier Board 5 Then use the instructions from the previous section to install BW968 and heatsink on the top of the COMe LINK1 debug card Screws...

Страница 28: ...onfigure the BIOS settings Default Configuration Most of the configuration settings are either predefined according to the Load Optimal Defaults settings which are stored in the BIOS or are automatica...

Страница 29: ...t is hour minute second The time is based on the 24 hour military time clock For example 1 p m is 13 00 00 Hour displays hours from 00 to 23 Minute displays minutes from 00 to 59 Second displays secon...

Страница 30: ...PU Configuration This section allows you to configure the CPU Intel Speed Step Enable Disable Intel Speed Step Technology Turbo Mode This field is used to enable or disable processor turbo mode After...

Страница 31: ...elect the primary display Auto integrated graphics display IGD or PCIe graphics card PCIe LCD Panel Type Select the LCD panel resolution LCD Panel Color Depth Select the LCD panel color depth 18 bit 2...

Страница 32: ...ce Disabled Azalia will be unconditionally disabled Enabled Azalia will be unconditionally enabled SATA Configuration This section lets you select the SATA controller and the type of hard disk drive i...

Страница 33: ...CI PreBoot Support Disabled Disable the USB XHCI PreBoot Support PCI Express Configuration This section configures settings relevant to PCI Express root ports PCIe Speed Select the speed of the PCI Ex...

Страница 34: ...ings Disable Disable this COM port Enable Enable this COM port COM Port 1 to COM Port 2 Configure the settings for each COM port WDT Enable or disable the watchdog function A counter will appear if yo...

Страница 35: ...than one character This section allows you to configure the Trusted Platform Module TPM on the system Boot Numlock Select the power on state for Numlock Boot Type Select the boot type The options are...

Страница 36: ...rnet adaptor supporting PXE Preboot Execution Environment Exit Exit Saving Changes Select this field and then press Enter to exit the system setup and save your changes Load Optimal Defaults Select th...

Страница 37: ...ease to be effective Note a You can take advantage of flash tools to update the default configuration of the BIOS SPI ROM to the latest version anytime b When the BIOS IC needs to be replaced you have...

Страница 38: ...enhance the performance of the system board Insert the DVD into a DVD ROM drive The autorun screen Mainboard Utility DVD will appear If after inserting the DVD Autorun did not automatically start whi...

Страница 39: ...www dfi com Chapter 5 Supported Software 39 Chapter 5 Auto Run Page For Windows 7...

Страница 40: ...ipset can be recognized and configured properly in the system To install the utility click Intel Chipset Software Installation Utility on the main menu 2 Read the license agreement then click Yes 1 Se...

Страница 41: ...system rebooted the screen will turn blank for 1 to 2 minutes while WinSAT is running before the Windows 7 Windows 8 1 Windows 10 desktop appears The blank screen period is the time Windows is testing...

Страница 42: ...puter now then click Finish Restarting the system will allow the new software installation to take effect Audio Drivers To install the driver click Audio Drivers on the main menu Intel LAN Drivers To...

Страница 43: ...l Mode Driver For Windows 7 only To install the driver click Kernel Mode Driver Framework on the main menu 1 Click Yes to install the update 2 The update is installed now 4 Click Install to begin the...

Страница 44: ...tall the driver click Intel Trusted Execution Engine Driver on the main menu 1 Tick I accept the terms in the License Agreement and then click Next 2 The step shows the components which will be instal...

Страница 45: ...complete HW Utility HW Utility provides information about the board Watchdog and DIO To access the utility click HW Utility on the main menu Note If you are using Windows 7 or later versions you need...

Страница 46: ...stalled The HW Utility icon will appear on the desktop Double click the icon to open the utility BW968 Note Note The screenshot displayed above is for illustrative purpose only and may not resemble th...

Страница 47: ...l USB 3 0 Driver on the main menu 2 Read the license agreement then click Yes 1 Setup is ready to install the driver Click Next 3 Go through the readme docu ment for more installation tips then click...

Страница 48: ...Intel Serial IO Driver on the main menu 1 Setup is ready to install the driver Click Next 2 Read the license agreement care fully Click I accept the terms in the Li cense Agreement then click Next 4...

Страница 49: ...To install the reader click Adobe Acrobat Reader 9 3 on the main menu 1 Click Next to install or click Change Destination Folder to select another folder 2 Click Install to begin installation 3 Click...

Страница 50: ...or s power switch is on 2 Check that one end of the monitor s power cord is properly attached to the monitor and the other end is plugged into a working AC outlet If necessary try another outlet 3 Che...

Страница 51: ...attaching it to a serial port that is work ing and configured correctly If the serial device does not work either the cable or the serial device has a problem If the serial device works the problem ma...

Страница 52: ...ode Value Description POST_BDS_NO_BOOT_DEVICE F9 No Boot Device POST_BDS_JUMP_BOOT_SECTOR FE Try to Boot with INT 19 ACPI 8 Bit POST Code Values Functionality Name POST Code Value Description ASL_ENTE...

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