Denon DN-S5000, Руководство по обслуживанию

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28
28 DN-S5000
128M SDRAM
(IC402, 403)
Pin Assignment
W29EE011P (IC507)
54
27 28
TOP VIEW
1
Description Pin No. Pin Name Function
22, 23~26, A0~A11 Address Multiplexed pins for row and column address.
29~35 Row address: A0~A11. Column address: A0~A8.
20, 21 BS0, Bank Select Select bank to activate during row address latch time, or bank to
BS1 read/write during address latch time.
2, 4, 5, 7, 8, DQ0~ Data Input/Output Multiplexed pins for data output and input.
10,11, 13, 42, DQ15
44,45, 47, 48,
50, 51, 53
19 CS# Chip Select Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
18 RAS# Row Address Strobe Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
17 CAS# Column Address Strobe Referred to RAS#
16 WE# Write Enable Referred to RAS#
15, 39 UDQM/ input/output mask The output buffer is placed at Hi-A (with latency of 2) when DQM is
LDQM sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock.
37 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
1, 14, 27 Vcc Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
28, 41, 54 Vss Ground Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49 VccQ Power (+3.3V) for I/O buffer Separated power from Vcc, used for output buffers to improve noise.
6, 12, 46, 52 VssQ Ground for I/O buffer Separated ground from Vss, used for output buffers to improve noise.
36, 40 NC No Connection No Connection
1 2 3 4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30 31 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1 DQ2
GND
DQ3 DQ4 DQ5 DQ6
A14
A13
A8
A9
OE
DQ7
A12 A15 A16 NC VDD WE NC
A10
CE
A11
TOP
VIEW
CE
OE
WE
DQ0
:
DQ7
A0
.
.
.
.
.
.
.
A16
V
DD
V
SS
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
A0 - A16
DQ0 - DQ7
CE
OE
WE
VDD
GND
NC
Name Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Terminal Function