Denon AVR-S510BT, Руководство по обслуживанию

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83
ADV7623 Hardware Manual
Rev. 0 – March 2010
18
Confidential NDA required
Location Mnemonic Type Description
D in the HDMI interface.
27 RXD_0+ HDMI Input Digital input channel 0 True of port D in
the HDMI interface.
28 CGND Ground TVDD and CVDD Ground
29 RXD_1- HDMI Input Digital input channel 1 complement of port
D in the HDMI interface.
30 RXD_1+ HDMI Input Digital input channel 1 true of port D in the
HDMI interface.
31 TVDD Power Receiver terminator supply voltage (3.3 V)
32 RXD_2- HDMI Input Digital input channel 2 complement of port
D in the HDMI interface.
33 RXD_2+ HDMI Input Digital input channel 2 true of port D in the
HDMI interface.
34 CVDD Power Receiver comparator supply voltage (1.8V)
35 CGND Ground TVDD and CVDD Ground
36 TXPVDD Power 1.8 V Power Supply for Digital and I/O
Power Supply. These pins supply power to
the digital logic and I/Os. They should be
filtered and as quiet as possible.
37 TXPLVDD Power 1.8 V Power Supply.
38 TXGND Ground TXPVDD Ground
39 TXPGND Ground TXPLVDD Ground
40 EXT_SWING Analog Input Sets Internal Reference Currents. Place 887
Ω resistor (1% tolerance) between this pin
and ground.
41 HPD_ARC- Analog Input Hot Plug Detect Signal. This indicates to
the interface whether the receiver is
connected. Supports 1.8 V to 5.0V CMOS
logic levels.
42 ARC+ Analog Input Audio return channel input
43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin
serves as the master to the DDC bus.
Supports a 5 V CMOS logic level.
44 TXDDC_SCL Digital Input Serial Port Data Clock to Receiver. This pin
serves as the master clock for the DDC bus.
Supports a 5 V CMOS logic level.
45 TXAVDD Power 1.8V power supply for TMDS outputs
46 TXGND Ground TXAVDD Ground
47 TXC- HDMI Output Differential Clock Output. Differential
clock output at the TMDS clock rate;
supports TMDS logic level.
48 TXC+ HDMI Output Differential Clock Output. Differential
clock output at the TMDS clock rate;
supports TMDS logic level.