34
34
AVR-3805 / AVC-3890
PCM1791 Terminal Function
DESCRIPTIONS
Pin
No.
Pin Name
PCM1791 (AD: IC523~526)
1
LRCK
I
Left and right clock (f
s
) input for normal operation. WDCK clock input in external DF mode.
Connected to GND in DSD mode*
2
BCK
I
Bit clock input. Connected GND for DSD mode*
3
DATA
I
Serial audio data input for normal operation. L-channel audio data input for external DF and DSD
modes*
4
MUTE
I
Analog output mute control for normal operation. R-channel audio data input for external DF and
DSD modes*
5
SCKI
I
System Clock Input. BCK (64f
s
) clock input for DSD mode*
6
RST
I
Reset*
7
V
DD
—
Digital power supply, +3.3 V
8
DGND
—
Digital ground
9
AGNDF
—
Analog ground (DACFF)
10
V
CC
R
—
Analog power supply (R-channel DAC), +5.0 V
11
AGNDR
—
Analog ground (R-channel DAC)
12
V
OUT
R-
O
R-channel analog voltage output-
R-channel analog voltage
Internal bias de-coupling pin
Analog power supply (internal bias), +5.0 V
Analog ground (internal bias)
L-channel analog voltage
L-channel analog voltage output-
Analog ground (L-channel DAC)
Analog power supply (L-channel DAC), +5.0 V
Analog power supply ( DACFF), +5.0 V
Zero flag for R-channel
Zero flag for L-channel
24
RSV
—
Reserved pin. It must be open.
25
MDO
O
Serial data output for function control register**
26
MDI
I
Serial data input for function control register*
27
MC
I
Shift clock for function control register*
28
MS
I
Mode control chip select and latch signal*
I/O
1
2 8
2
2 7
3
2 6
5
4
2 5
6
2 4
7
2 3
8
2 2
9
2 1
1 0
2 0
1 1
1 9
1 2
1 8
1 3
1 7
1 4
L R C K
B C K
D ATA
S C K I
M U T E
R S T
V
D G N D
A G N D F
V R
A G N D R
V R -
V R +
V
1 5
1 6
M S
M C
M D O
M D I
R S V
Z E R O L
Z E R O R
V F
V L
A G N D L
V L-
V L +
A G N D C
V C
D D
C O M
C C
C C
C C
C C
O U T
O U T
O U T
O U T
T O P V I E W
*
Schmitt trigger input, 5V tolerant.
**
Tristate output.
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