Dell EqualLogic PS4100E, Руководство по настройке

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March 2013 Dell EqualLogic Configuration Guide v14.1 8-80
If you are using switches that do not support a stacking mode then you must use the straight
interconnect uplink pattern shown in Figure 29. Note the following design differences between the
split uplink pattern in Figure 28 and the straight uplink pattern in Figure 29:
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A LAG is used to create the connection between 1Gb SW#1 and 1Gb SW#2 .
•
A high rapid spanning tree link cost is assigned to the 1Gb switch LAG (note the location of the
RSTP blocked path in Figure 29). Doing this prevents 10Gb inter-switch traffic from having to
pass through the 1Gb switch LAG.
Figure 29 Mixed speed redundant SAN using straight interconnect between 1Gb and 10Gb switches
8.2 Mixed speed SAN best practices
The following list summarizes the important SAN design considerations for integrating 10Gb
EqualLogic arrays into existing 1Gb EqualLogic SANs.
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When integrating 10Gb switches into your existing 1Gb environment, how you interconnect the
mixed speed switches (split vs. straight uplink) does not have a significant impact on performance
as long as the uplinks are sized appropriately to your workloads.
•
If your 1Gb switches are configured as a stack then you should use the split interconnect
pattern shown in Figure 28 by default.
•
If your 1Gb switches are not stacked, then you must use the straight interconnect pattern
shown in Figure 29.
•
When connecting 1Gb switches and 10Gb switches together you must always be aware of where
Rapid Spanning Tree is going to block links to make sure that 10Gb traffic (i.e. EqualLogic inter-
array data flow) never crosses the 1Gb switch.
•
You must configure pools and volumes in a way that minimizes impact to IO performance.