H O S T I N T E R F A C E
Data Device Corporation
DS-BU-67301B-G
1/14
83
Figure 43. Synchronous, Multiplexed Address - 32-bit Sequential Burst Memory Read
Transfer Timing
Figure 43 Notes:
1. With nSELECT asserted low and valid address presented on CPU_DATA, a
positive pulse on the ADDR_LAT input satisfying t
ALS
and T
AHL
will result in the
Total-AceXtreme®
latching the starting address for the sequential burst. One
host clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low)
while nSELECT remains asserted (low) initiates the sequential burst transfer.
nSELECT must be asserted low through the remainder of the burst cycle. The
nDATA_RDY output is initially asserted low on the same host clock cycle
when the
Total-AceXtreme
drives the first valid data word on the data bus.
CPU_nLAST must be asserted high until the last word is to be read. On the
rising host clock edge following CPU_nLAST asserting low, the last word is
removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted
(high). At this time (or later) nSELECT must be de-asserted high, completing
the burst read transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory word(s) are valid for this transfer. If either or both these bits is ‘0’,
then the corresponding 16-bit word(s) will return a value of ‘0000’. These
inputs should be tied high if unused.
3. Unless the
Total-AceXtreme
command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
HOST_CLK
nDATA_RDY
CPU_DATA
CPU_WORD_EN[1:0]
RD_nWR
MEM_nREG
ADDR_LAT
nDATA_STRB
nSELECT
CPU_nLAST
CPU_nSTOP
tAH
tCLK
tDD
tRDD
Data
Data
Data
Data
Data
Data
Data
Data
tRDD
tCS
tDH
tCH
tLS
tAS
tALS
tALH
tAH
tAH
tAH
tSS
tSH
Address
tLH
tLS
tLH
tSHC
tAS
tAH
tAS
tAS
tWait
