Data Translation DT9800 Series, Руководство пользователя

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Principles of Operation
29
2
2
2
2
2
2
2
2
2
The sample rate is determined by the frequency of the A/D sample
clock divided by the number of entries in the channel-gain list; refer
to
page 23 for more information on the A/D sample clock. The
conversion rate of each scan is determined by the frequency of the
internal retrigger clock. The internal retrigger clock is the Triggered
Scan Counter on the board; the Triggered Scan Counter is a 24-bit
counter with a 12 MHz clock.
Figure 4 illustrates triggered scan mode. In this example, post-trigger
analog input data is acquired on each clock pulse of the A/D sample
clock until the channel-gain list has been scanned once; then, the
board waits for the retrigger event. When the retrigger event occurs,
the board scans the channel-gain list once again, acquiring data on
each pulse of the A/D sample clock. The process repeats
continuously with every specified retrigger event.
Figure 4: Triggered Scan Mode
Specify the frequency of the internal retrigger clock using software.
The minimum retrigger frequency is 0.75 Hz (0.75 Samples/s); the
maximum retrigger rate of each DT9800 Series function module is
listed in
Table 5 on page 30 .
Trigger event occurs;
data acquired for one
scan of the CGL.
Chan 0
Chan 1
Chan 2
A/D
Sample
Clock
Chan 0
Chan 1
Chan 2
Retrigger event occurs;
data acquired for one
scan of the CGL.
Board waits for
retrigger event.