Data Translation DT9800 Series, Руководство пользователя

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Principles of Operation
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Through software, specify the clock source as internal and the
frequency at which to pace the counter/timer operation (this is the
frequency of the clock output signal). The maximum frequency that
you can specify for the clock output signal is 750 kHz. For a 32-bit
cascaded counter, the minimum frequency that you can specify for
the clock output signal is 0.0028 Hz.
Gate Types
The active edge or level of the gate input to the counter enables
counter/timer operations. The operation starts when the clock input
signal is received. Specify the gate type in software.
DT9800 Series modules provide the following gate input types:
• None
−
A software command enables any specified
counter/timer operation immediately after execution. This gate
type is useful for all counter/timer modes; refer to
page 53 for
more information on these modes.
• Logic-low level external gate input
−
Enables a counter/timer
operation when the external gate signal is low, and disables the
counter/timer operation when the external gate signal is high.
Note that this gate type is used only for event counting,
frequency measurement, and rate generation; refer to
page 53 for
more information on these modes.
• Logic-high level external gate input
−
Enables a counter/timer
operation when the external gate signal is high, and disables a
counter/timer operation when the external gate signal is low.
Note that this gate type is used only for event counting,
frequency measurement, and rate generation; refer to
page 53 for
more information on these modes.