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7.Electrical Interface
© 2023 China Daheng Group, Inc. Beijing Image Vision Technology Branch 91
3.3V
Line2
FPGA INPUT2
1
6
2
5
3
4
Camera internal circuit
External circuit
Signal output
Power+
PWR
GND
NPN
Pull-up
resistor
Figure 7-21 NPN photoelectric sensor connected to Line2 input circuit (ME2S)
3.3V
Line2
FPGA INPUT2
1
6
2
5
3
4
Camera internal circuit
External circuit
Signal
output
Power+
PWR
GND
PNP
Pull-down
resistor
Figure 7-22 PNP photoelectric sensor connected to Line2 input circuit (ME2S)
When LIine2/3 is configured as input, pull-down resistor over 1K should not be used, otherwise the
input voltage of Line2/3 will be over 0.6V and logic 0 cannot be recognized stably
Input rising time delay: <2μs (0°C~45°C), parameter description as shown in Figure 7-23
Input falling time delay: <2μs (0°C~45°C), parameter description as shown in Figure 7-23
TRIGIN_F_DELAY
TRIGIN_R_DELAY
2V
0.8V
Line2
INPUT2
Figure 7-23 Parameter of Line2 input circuit