Daewoo DTL- 25G6F, Руководство по обслуживанию

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To protect the horizontal deflection transistor, the ho rizontal drive is switched off immediately when a power
failure ( “ Power-On Reset “ bit POR ) is detected.
The power failure may have corrupted the contents of the internal data registers, so the TDA8844 should be
started up again.
The TDA8844 has a separate supply input (pin 37) that only used as a clean supply voltage for thehorizontal
oscillator circuits.
Vertical synchronization
The vertical sawtooth generator drives the vertical output.
It uses an external capacitor at pin 51 and a current reference resistor at pin 52.
The TDA8844 vertical drive has differential current outputs for DC-coupled vertical output stage, like the TDA8351 .
At TDA8351 input pins 1 and 2 this current is converted into a drive voltage via a resistor.
Geometry processing
With the TDA8844 is possible to implement automatic geometry alignment, because all parameters are adjusted
via the I2C bus.
The deflection processor of the TDA8844 offers the following five controls;
- Horizontal shift
- Vertical slope.
- Vertical amplitude
- Vertical S-correction
- vertical shift
PAL/NTSC demodulation
The 0 and 90 reference signals from the VCXO are supplied to the HUE phase rotator; it’s outputs (H0, H90) are
supplied to the (B-Y) and (R-Y) burst demodulators respectively.
The demodulated burst from the (B-Y) demodulator supplies NTSC ident information to the ASM(IDN signal).
The demodulated burst from (R-Y) demodulator supplies PAL ident information to the ASM(IDP signal).
For correct demodulation of (R-Y) PAL burst and chroma signals, then the H90 signal requires 180 phase shift on
alternate lines. This is realised with the H/2 switch before the (R-Y) demodulator. It is not active during demodulation of
NTSC signals.
The (B-Y)/(R-Y) baseband signals are obtained from the chroma signal by the (B-Y)/(R-Y) demodulators, filtered and
supplied via the PAL/SECAM switch(PS) to the internal baseband delay line.
The demodulator gain ratio (B-Y)/(R-Y) is typically 1.78 in order to compensate for scaling in the transmitter.
For NTST applications it is possible to bypass the delay line via I2C bus command BPS; the gain is also corrected then
by a factor two.
The V
INT
and U
INT
signals from delay line outputs are fed to the YUV selection circuit(see YUV/RGB processing part).
SECAM demodulation
SECAM demodulation is realised with a PLL type demodulator.
When the VCXO is connected to pin 35 (controlled by XTS) and if a 4.43 MHz Xtal is present on that pin then SECAM
demodulation is possible. The auto tuning loop, consisting of PLL demodulator and oscillator, ensures that the PLL
oscillator is locked to the 4.43MHz Xtal frequency during calibration time in the vertical retrace period. The SECAM
reference voltage, generated at pin 16, is regulated in order that the PLL demodulator output is set to a reference voltage
derived from a stable bandgap voltage.
Outside calibration the oscillator remains tracking the SECAM chrominance resulting in the corresponding demodulated
voltage. This is delivered to the LF de-emphasis stage and to the line ident stage of the Automatic System Manager(IDS
switch(PS) to the baseband delay line. The bypass mode of the delay line is not possible for SECAM.
The V
INT
and U
INT
signals from delay line outputs are fed to the YUV selection circuit(see YUV/RGB processing part).