Daewoo DSL-19M1TC, Руководство по обслуживанию

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17
PD46
132 O Blue channel bit 6 (Odd) Blue channel bit 4 (Odd)
PD47 118 O Blue channel bit 7 (Odd) Blue channel bit 5 (Odd)
Note: In case of 24 Bit TTL Panels the RGB Odd Channel Outputs will not be used. In that case they can be
made available for other purposes as Address & Data from On-Chip Micro or Digital Video Input Data.
Table 8: Parallel/Serial ROM Interface
Pin Name No I/O Description
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 95
96
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115 O 256K x8 PROM Address. These pins also have bootstrap functionality.
For serial SPI ROM interface:
- ROM_ADDR17 will be Serial Clock (ROM_SCLK)
- ROM_ADDR16 will be Serial Data Output (ROM_SDO)
For 512K X 8 PROM, Address Signal A18 is available thru Pin # 44 which is GPIO10.
D7
D6
D5
D4
D3
D2
D1
D0 132
131
130
129
128
125
124
123 IO External PROM data input.
ROM_OEN 118 O External PROM data Output Enable.
ROM_SDI/
ROM_WEN 97 O External PROM data Write Enable (for In-System-Programming of FLASH) or Serial Data Input
(SDI) for SPI ROM interface.
ROM_SCSN/
ROM_CSN 94 O External PROM data Chip Select or Serial PROM Chip Select (ROM_SCSN) for SPI ROM
interface.
Table 9: Digital Power and Ground
Pin Name No I/O Description
RVDD_3.3 32 49 98 116 154 P Ring VDD. Connect to digital 3.3V.
CVDD_1.8 18 28 39 45 84 119 126 133 143 P Core VDD. Connect to digital 1.8V.
CRVSS 19 29 33 40 46 50 85 99 117 120
127 134 144 155 G Chip ground for core and ring.
Table 10: JTAG Boundary Scan
Pin Name No I/O Description
TCK 34 I JTAG Boundary Scan TCK signal
TDO 55 O JTAG Boundary Scan TDO signal
TDI 35 I JTAG Boundary Scan TDI signal. Pad has internal 50K pull-up resistor.
TMS 36 I JTAG Boundary Scan RST signal. Pad has internal 50K pull-up resistor.
TRST 37 I JTAG Boundary Scan TMS signal. Pad has internal 50K pull-up resistor.