Daewoo DSD-9251MA, Руководство по обслуживанию

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11
CIRCUIT OPERATING MANUAL
(2) Reset Section.
If the Low signal is read by Sti5518 Reset Pin, the Register value of all Sti5518 will be initialized.
There must be at least of 8 clock (37nsec) of Reset Time.
(3) Clock Section.
STI5518 has two PLL inside. Operative clocks are made by external clock with one unit of 27MHz. The two PLL are as
of ST20 PLL and MPEG PLL.
ST20 PLL produces 81MHz of system clock that is to be used in processor and peripheral equipment.
MPEG PLL produces audio decoder system clock, audio PCM clock, TS Demultiplexer and memory clock of SDRAM.
27MHz clock uses VCXO. Currency control is enabled by PWM OF Sti5518
PWM with the reference of the PCR
value of MPEG to set the exact initiative of MPEG. If this value is not appropriate the colors are not be seen on the
screen, or the screen will display broken features.
(4) PIO Structure.
Sti5518 supports PIO that back up 5 number of Ports (8bit) as of PIO0, PIO1, PIO2, PIO3 and PIO4. Some ports are
able to endow extra functions to PIO for flexible expansion in usage. Following chart shows Alternative Function Pin of
PIO.
PIO port 0
ASC0TxD or
Sc1DataOut
ASC0RxD or
Sc1DataIn
Not connected
Sc1Clk
(Sc1RST)
(Sc1CmdVcc)
ASC0Dir
(Sc1Detect)
PIO port 1
SSC0 MTSR
SSC0 MRST
SSC0 SCIK
CaptureIn1
CaptureIn2
ASC1TxD
ASC1RxD
ASC3TxD
PIO port 2
ASC2TxD
or Sc0DataOut
ASC2RxD
or Sc0DataIn
Not connected
Sc0Clk
CompareOut0
(Sc0RST)
(Sc0CmdVcc)
Not connected
CaptureIn0
(Sc0Detect)
PIO port 3
TriggerIn
TriggerOut
PIO port 4
CompareOut1
(IROut)
CaptureIn3
ASC3RxD
not_Rst
tRSTLRSTH
Min 8x37nsec
Feature 6. Reset Timing
Chart 2. PIO Alternate Functions.
Alternative function of PIO pins
Port bit
0
1
2
3
4
5
6
7