Daewoo DDT-21H9ZDF(21"), Руководство по обслуживанию

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Service Manual CP-099/FS
5-3-19 Vertical and East/West Deflection
The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor (FP).
The algorithm uses a chain of accumulators to generate the required polynomial waveforms. To produce the deflection
waveforms, the accumulators are initialised at the beginning of each field. The initialisation values must be computed
by the TV control processor and ar e written to the front-end once.
5-3-20 EHT Compensation
The vertical waveform can be scaled according to the average beam current. This is used to compensate the effects of
electric high-tension changes due to beam current variations. EHT compensation for East/West deflection is done with
an offset corresponding to the average beam current.
5-3-21 Reset Function
Reset of all VDP functions is performed by the RESQ pin. When this pin becomes active, all internal registers and
counters are lost.
5-3-22 Standby and Power-On
The VDP does not have a standby mode. To disable all the analogue and digital video functions, it is necessary to
switch off the supplies for analogue front-end (VSUP AF ), analogue back-end (VSUP AB ) and digital circuitry
(VSUP D ).
5-4- Microcontroller
5-4-1 Introduction
The TV controller basically consists of the CPU, RAM, ROM, and a number of peripheral modules.
For instance:
– a memory banking module is included to allow access to more than 64 kB memory.
– a bootloader software is included to allow in-system-downloading of external code to Flash memory via the I 2 C
interface.
The TV controller runs the complete software necessary to control a TV set. The software includes control of the audio,
video, OSD, and text processors on chip, as well, as control of external devices like tuner or stereo decoder.
Communication between the TV controller and external devices is done either via I 2 C bus interface or via program-
mable port pins. The TV Controller is clocked with f OSC = f XTAL /2.
5-4-2 CPU
The CPU is fully compatible to WDC’s W65C02 micro-processor. The processor has 8-bit registers/accumulator, an 8-
bit data bus, and a 16-bit address bus.
configuration
Stand by TV ON
5 Power Push Pull High Push Pull Low Switch OFF / ON SMPS
8 IR High impedance High impedance Interrupt input
10 SC SW High impedance High impedance SCART 1 slow switching –
ADC input
9 Mute Push Pull Push Pull Low = Mute active
IF IC 3PIN(14" MODEL)
6 LED High Low
1
2 KEY 1
KEY 2 High impedance High impedance Keyboard input – ADC
input
7 OCP High impedance High impedance Over Current Protection –
Switch the set to Std by if < 2.
5-4-3 - Controller I/O pin configuration and function
There exist different kinds of ports. The universal ports serve as digital I/O and have additional special input and output
functions. A subset of the universal ports serves as input for the analogue-to-digital converter.
- Controller I/O pin configuration and function table
pin
name
description
To reduce power consumption in stand by mode all ports not used are configured in high impedance mode.