Daewoo 14C5, Руководство по обслуживанию

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IC DESCRIPTION
1. TDA9361 : TV signal processor - Teletext decoder with embedded
µ
-Controller.
TDA9381 : TV signal processor - with embedded
µ
-Controller.
TV-signal Processor
• Multi-standard vision IF circuit with alignment-free PLL demodulator
• Internal (switchable) time-constant for the IF-AGC circuit
• Mono intercarrier with a selective FM-PLL demodulator which can be switched to the different FM sound frequencies
(5.5 / 6.0 / 6.5 MHz)
• Source selection between 'Internal' CVBS and external CVBS or Y/C signals
• Integrated chrominance trap circuit
• Integrated luminance delay line with adjustable delay time
• Asymmetrical ‘delay line type’ peaking in the luminance channel
• Black stretching for non-standard luminance signals
• lntegrated chroma band-pass filter with switchable centre frequency
• Only one reference (12 MHz) crystal required for the
µ
-Controller, Teletext and the colour decoder
• PAL / NTSC or multistandard colour decoder with automatic search system
• Internal base-band delay line
• RGB control circuit with 'Continuous Cathode Calibration', white point and black level off set adjustment so that the colour
temperature of the dark and the bright parts of the screen can be chosen independently.
• Linear RGB or YUV input with fast blanking for external RGB/YUV sources. The Text/OSD signals are internally supplied
from the
µ
-Controller/Teletext decoder
• Contrast reduction possibility during mixed-mode of OSD and Text signals
• Horizontal synchronisation with two control loops and alignment-free horizontal oscillator
• Vertical count-down circuit
• Vertical driver optimised for DC-coupled vertical output stages
• Horizontal and vertical geometry processing
µ
-Controller
• 80C51
µ
-controller core standard instruction set and timing
• 1
µ
s machine cycle
• 64Kx8-bit programmed ROM
• 3 - 12Kx8-bit Auxiliary RAM (shared with Display and Acquisition)
• Interrupt controller for individual enable/disable with two level priority
• Two 16-bit Timer/Counter registers
• watchdog timer
• Auxiliary RAM page pointer
• 16-bit Data pointer
• IDLE and Power Down (PD) mode
• 8-bit A/D converter
• 4 pins which can be programmed as general I/0 pin or ADC input.
APPENDIX