10
CIRCUIT OPERATION MANUAL
(1) Structure
STi5518 is a 1 chip including 32bit RISC CPU, A/V Demux, Video Encoder, Multi PIO and Cache RAM for the use o
DVB and DSS Set Top.
Followings are summary of distinctive features of each Block.
Enhanced capability with 32bit VL-RISC CPU Core of 81MHZ clock.
Supporting Bandwidth of 200MB/S using internal 2KB SRAM buffer and 2KB DCACHE.
Video Decoder is attached inside supported by MPEG-2 MP@ML and Letter Box.
MPEG Layer1 and 2 Audio Decoder are stored inside.
Providing interface external AC3 Decoder.
Supporting 2 - 8bit/pixel OSD.
Internally stored Video Encoder for the output of RGB, CVBS and Y/C Video
Enhanced CPU and Decoder capability boosted by 64Mbit SDRAM.
Backing External Surrounding Interface Memories. ( 4 Banks )
Able to use Hardware DMUX, input Serial and to support 32Pid.
Boosting 8 Level INT.
Supporting DMA and other multi PID.
2
MPEG
DMAs
Serial
IEEE
1394
Hardware
transport
strearn
demux
2
Kbytes
Instruction
cache
2K
Data
cache
and
2K
SRAM
OS-Link
2
UART
1
I
2
C
PIO
3
PWM
Diagnostic
controller
and
systems
services
SDAV
interface
Block
move
DMA
ST20
CPU
Interrupt
controller
EMI
2
SmartCard
interfaces
(ASC)
MPEG
audio
decoder
AC-3
I/F
MPEG
video
decoder
PAL/NTSC
Encoder
Teletest
interface
Feature 5. Sti5518 Block Diagram
3. Peripheral device of STi5518
Block move
DMA
2 MPEG
DMAs
Serial IEEE 1394
SDAV
interface
Hardward
transport
strearn demux
2 Kbytes
Instruction
cache
2K Data
cache and
2K SRAM
OS-Link
2 UART
PIO
3 PWM
Diagnostic
controller and
systems services
ST20
CPU
Interrupt
controller
EMI
2 SmartCard
interfaces(ASC)
MPEG audio
decoder AC-3 I/F
MPEG
Video
decoder
PAL/NTSC
Encoder
Teletest
interface
Sit5518 Block Diagram
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Содержание DSD-9251EAV
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Страница 57: ...56 PARTS PLACEMENT ARRANGEMENT 9251 FRONT PCB All manuals and user guides at all guides com...
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