Cypress Traveo S6J32E Series, Руководство пользователя

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Document Number: 002-10689 Rev *H Page 78 of 166
S6J32E, S6J32F, S6J32G Series
8.4.2 Sub Clock Timing
(Condition: See 8.2. Operation Assurance )
Parameter Symbol
Pin
Name
Conditions
Value
Unit Remarks
Min Typ Max
Source oscillation
clock frequency
F
CL
X0A, X1A - - 32.768 - kHz
Source oscillation
clock cycle time
t
LCYL
X0A, X1A - - 30.52 - µs
−
X0A and X1A clock timing
X0A
t
LCYL
8.4.3 Internal Clock Timing

This section shows the characteristics for internal clock timing at the current stage.

In the column symbol, the same clock names as described in
‘Chapter 5: Clock System’ of the Platform hardware manual are
used.

Corresponding functions for these clocks are described in
‘Chapter 5: Clock Configuration’ of the S6J3200 series hardware
manual.
(Condition: See 8.2. Operation Assurance )
Table 8-1: Assured Combination of Clock Frequency
Symbol
Max Value Combination
Unit Remarks
Max *1 Max *2 Max *3
F
SSCG0
232
(464)
200
(800)
160
(640)
MHz SSCG0 output clock
F
SSCG1
200
(800)
200
(800)
200
(800)
MHz SSCG1 output clock
F
SSCG2
200
(800)
200
(800)
200
(800)
MHz SSCG2 output clock
F
SSCG3
400
(800)
400
(800)
400
(800)
MHz SSCG3 output clock
F
PLL0
240
(480)
200
(800)
200
(800)
MHz PLL0 output clock
F
PLL1
400
(800)
400
(800)
400
(800)
MHz PLL1 output clock
F
PLL2
200
(800)
200
(800)
200
(800)
MHz PLL2 output clock
F
PLL3
240
(480)
240
(480)
240
(480)
MHz PLL3 output clock
F
CLK_CPU0
240 200 160 MHz
F
CLK_SHE
240 200 160 MHz
F
CLK_FCLK
80 66.7 80 MHz
F
CLK_ATB
120 100 80 MHz
F
CLK_DBG
120 100 80 MHz
F
CLK_HPM
120 200 160 MHz