Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 23:Stereo Audio DAC
884 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.9.
Frequency of CLKPI and CLKDA
Please set the clock that meets the following requirements to CLKPI (bus clock) and sampling clock
CLKDA (CLKDACI is divides)
CLKPI ≥ CLKDA / 17
FIFO operates with CLKPI, and the portion of analog circuit does with CLKDA. Then, CLKDA should be
fast enough for data to be transferred from FIFO to analog circuit.
3.10.
Sampling Frequency and Oversampling Setting of D/A Converter
The input of analogDAC is decided by setting DAOSR_OSR and DAOSR_DACCLK. Table 4 and Table 5
show the example of the set value to DAOSR_OSR and DAOSR_DACCLK.
Table 5 shows System Clock and over sampling ratio.
Table 6 shoes Setting of dividing frequency.
Table 5 System Clock and over Sampling Ratio
Sampling frequency
(fs)[kHz]
pin setting
OSR system clock frequency
OSR[1:0]
8, 11.025, 12 11 512 512fs
16, 22.05, 24 10 256 256fs
32, 44.1, 48 01 128 256fs
Notes:
−
384fs is not supported.
−
OSR[1:0]=00 is not supported.
−
OSR[1:0] is OSR field of the DAOSR register.
Table 6 Setting of Dividing Frequency
Fs
256fs 512fs
CLKDAO
DACC
LK
CLKDACI CLKDAO DACCLK CLKDACI
8kHz 2.048MHz
1/1 2.048 MHz
4.096MHz
1/1 4.096 MHz
1/2 4.096 MHz 1/2 8.192 MHz
1/8 16.384 MHz 1/8 32.768 MHz
1/10 20.48 MHz 1/10 40.96 MHz
1/16 32.768 MHz 1/16 65.536 MHz
11.025kHz 2.8224MHz
1/1 2.8224 MHz
5.6448MHz
1/1 5.6448 MHz
1/2 5.6448 MHz 1/2 11.2896 MHz
1/8 22.5792 MHz 1/8 45.1584 MHz
1/10 28.224 MHz 1/10 56.448 MHz
1/16 45.1584 MHz 1/16 90.3168 MHz
12kHz 3.072MHz
1/1 3.072 MHz
6.144MHz
1/1 6.144 MHz
1/2 6.144 MHz 1/2 12.288 MHz
1/8 24.576 MHz 1/8 49.152 MHz
1/10 30.72 MHz 1/10 61.44 MHz
1/16 49.152 MHz 1/16 98.304 MHz