CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
737
4.82.
Receive Over Runs Register (ETHERNETn_rx_overruns)
Description Receive Over Runs register is shown.
REGISTER_NAME
ETHERNETn_rx_overruns
OFFSET
0x1A4
ACCESS_SIZE
W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET
31
30
29
28
27
26
25
24
BIT_NAME
Reserved
ACCESS_TYPE
R0,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
23
22
21
20
19
18
17
16
BIT_NAME
Reserved
ACCESS_TYPE
R0,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
15
14
13
12
11
10
9
8
BIT_NAME
Reserved
count[9:8]
ACCESS_TYPE
R0,WX
R,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
0x0
BIT_OFFSET
7
6
5
4
3
2
1
0
BIT_NAME
count[7:0]
ACCESS_TYPE
R,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
[bit31:10] Reserved
Always read "0". Writing has no effect.
[bit9:0] count: Receive over runs
A 10-bit register counting the number of frames that are address recognized but were not copied to
memory due to a receive over run.
Содержание S6J3200 Series
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