Cypress S6J3200 Series, Руководство пользователя

Страница: 508 / 1355

CHAPTER 20:Sound Mixer
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 507
Notes:
−
The following accesses cause the slave error response.
−
1) When the access destination is an address that does not exist in the memory map
−
2) The write access was done to the read only register.
−
3) When the access size is not supported.
−
(For example it accessed MXWFGnDADR/MXPMISnDADR with 8bit or 16bit) n=0 to 4
3.8.
AHB Master Interface
Mixer macros provide an AHB master interface for interfacing with subordinate macros. AHB Master
interface specifications are shown in Table 3-5.
Table 3-5 AHB Master interface
Item Table_Header
Burst transfer not support
Protection control not support
Response OKAY and ERROR only
Access size 8,16,32bit only
Width of address 13bit
Notes:
−
When an ERROR response is received by transfer control from the CPU interface, an error
response is transferred to the CPU interface.
−
Information about the operation when an error response is received during mixer macro
self-operation is stored in the information register and interrupt occurs.
3.9.
Input Buffer (FIFO)
Mixer macros provide a 5-channel input buffer for PCM/IS2 input. The input buffer is configured with one
Dual Port RAM, and a one-channel 32-word area is configured by address segmentation.
The input buffer is accessed via the channel-use MXPMISnDADR0-15(n=0 to 4) register. Since access of
the MXPMISnDADR0-15(n=0 to 4) register results in FIFO operation of the internal buffer, storage is in
access sequence regardless of the access address. The configuration of the input buffer is shown in
Table 3-6.
Table 3-6 Outline of input Buffer
Item Description
Width of data 32bit
Width of address 7bit
Depth 160(32×5ch)
Composition Dual Port RAM