S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
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Figure 1-7 Example Write Operation
Start of writing
Read internal address (Dummy)
Read internal address
Timing limit
(TLOV bit)
Read internal address
Last address
End of writing
Next address
Inverted data
1
No
Yes
Write error
:
Verify with a hardware sequence flag.
Data polling
(DPOL bit)
0
Data polling
(DPOL bit)
Data
Inverted data
Data
Set the ASZ bit of Flash access size
register (FASZR) to "0b01"
Read Flash access size register (FASZR)
(Dummy)
Write command sequence
1. Addr:000X_XAA8 Data:XXAA
2. Addr:000X_X554
Data:XX55
3. Addr:000X_XAA8 Data:XXA0
4. Write Address
Write Data
Read Flash access size register (FASZR)
(Dummy)
Set the ASZ bit of Flash access size
register (FASZR) to "0b10"
Notes:
−
See Section "
" for details on the write command.
−
The address notations in command sequences only show the lower 12 bits. The upper 20bits should be set to any
address within the address range of the target flash memory. When the address outside the flash address range is
specified, the command sequence would not operate correctly since the flash memory cannot recognize the
command.
−
Because the value of the DPOL bit of the hardware sequence flags changes at the same time as the TLOV bit, the
value needs to be checked again even if the TLOV bit is "1".
−
The toggle operation stops at the same time as the TOGG bit and TLOV bit of the hardware sequence flags change
to "1". Therefore, even if the TLOV bit is "1", the TOGG bit needs to be checked again.
−
Although the flash memory can be written in any sequence of addresses regardless of crossing sector boundaries,
only a single half-word of data can be written with each write command sequence. To write multiple pieces of data,
issue one write command sequence for each piece of data.
−
All commands issued to the flash memory during the write operation are ignored.
−
If the device is reset while the write is in progress, the data that is written is not guaranteed.
