Document Number: 002-00833 Rev. *L
Page 49 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
10.9
AC Characteristics
10.9.1
AC Characteristics–Synchronous Burst Read
Notes:
1. Not 100% tested.
2. If OE# is disabled before CE# is disabled, the output goes to High-Z by t
OEZ
.
If CE# is disabled before OE# is disabled, the output goes to High-Z by t
CEZ
.
If CE# and OE# are disabled at the same time, the output goes to High-Z by t
OEZ
.
3. AVD can not be low for 2 subsequent CLK cycles.
Figure 13. Synchronous Read Mode - ADM Interface
Parameter (Notes)
Symbol
83 MHz
104 MHz
108 MHz
Unit
Clock Frequency
CLK
Min
DC (0) for operations other than continuous and 32
byte synchronous burst.
120 in 32 Byte burst
1000 in continuous burst
KHz
Clock Cycle
t
CLK
Min
12
9.6
9.26
ns
CLK Rise Time
t
CLKR
Max
2.5
1.92
1.852
ns
CLK Fall Time
t
CLKF
CLK High or Low Time
t
CLKH/L
Min
5
4
3.86
ns
Internal Access Time
t
IA
Max
75
72.34
ns
Burst Access Time Valid Clock to Output
Delay
t
BACC
Max
9
7.6
6.75
ns
AVD# Setup Time to CLK
t
AVDS
Min
4
3.38
ns
AVD# Hold Time from CLK
t
AVDH
Min
3
2.89
ns
Address Setup Time to CLK
t
ACS
Min
4
2.89
ns
Address Hold Time from CLK
t
ACH
Min
5
4.82
ns
Data Hold Time from Next Clock Cycle
t
BDH
Min
3
2
2
ns
Output Enable to Data
t
OE
Max
15
ns
CE# Disable to Output High-Z
t
CEZ
Max
10
ns
OE# Disable to Output High-Z
t
OEZ
Max
10
ns
CE# Setup Time to CLK
t
CES
Min
4
3.38
ns
CLK to RDY valid
t
RACC
Max
9
7.6
6.75
ns
CE# low to RDY valid
t
CR
Max
10
ns
AVD# Pulse Width
t
AVDP
Min
6
ns
DC
DD
OE#
A/DQ15–
A/DQ0
Amax–
A16
AC
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVDP
t
ACH
t
OE
t
BDH
DE
DB
7 cycles for initial access is shown as an illustration.
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
BACC
t
CR
t
IA
AC
t
AVDH
