Document Number: 002-00833 Rev. *L
Page 17 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
7.
Device Operations
This section describes the read and write bus operations, program, erase, simultaneous read/write, handshaking, and reset features
of the Flash devices.
The address space of the Flash Memory Array is divided into banks. There are three operation modes for each bank:
Read Mode
Embedded Algorithm (EA) Mode
Address Space Overlay (ASO) Mode
Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.
In Read Mode a Flash Memory Array bank may be read by simply selecting the memory, supplying the address, and taking read
data when it is ready. This is done by asynchronous or burst accesses from the host system bus. The CU puts all banks in Read
mode during Power-on, a Hardware Reset, after a Command Reset, or after a bank is returned to Read mode from EA mode.
During a burst read access valid read data is indicated by the RDY signal being High. When RDY is Low burst read data is not valid
and wait states must be added. The use of the RDY signal to indicate when valid data is transferred on the system data bus is called
handshaking or flow control.
EA and ASO modes are initiated by writing specific address and data patterns into command registers (see
).
The command registers do not occupy any memory locations; they are loaded by write bus cycles with the address and data
information needed to execute a command. The contents of the registers serve as input to the Control Unit (CU) and the CU dictates
the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device
in an unknown state, in which case the system must write the reset command to return all banks to Read mode.
The Flash memory array data in a bank that is in EA mode, is stable but undefined, and effectively unavailable for read access from
the host system. While in EA mode the bank is used by the CU in the execution of commands. Typical command operations are
programming or erasing of data in the Flash array. All other banks are available for read access while the one bank is in EA mode.
This ability to read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write
(SRW) and allows for continued operation of the system via the reading of data or code from other banks while one bank is
programming or erasing data as a relatively long time frame background task. Only a status register read command can be used in
a bank in EA mode to retrieve the EA status.
While any one of the overlay address spaces are overlaid in a bank (entered) that bank is in ASO mode and no other bank may be
in EA or ASO mode. All EA activity must be completed or suspended before entering any ASO mode. A command for entering an EA
or ASO mode while another bank is in EA or ASO mode will be ignored.
While an ASO mode is active (entered) in a bank, a read for Flash array data to any other bank is allowed. ASO mode selects a
specific sector for the overlaid address space. Other sectors in the ASO bank still provide Flash array data and may be read during
ASO mode.
While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration Register respectively may be
programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The
ID/CFI and factory portion of the SSR ASO is not customer programmable. An attempt to program in these areas will fail.
7.1
Asynchronous Read
The device defaults to reading array data asynchronously after device power-up or hardware reset. The device is in the
Asynchronous mode when Bit 15 of the Configuration register is set to '1'. To read data from the memory array, the system must first
assert CE# and AVD# to V
IL
with WE# at V
IH
and a valid address.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable access time (t
CE
) is the
delay from stable CE# to valid data at the outputs. See
10.9.2, AC Characteristics–Asynchronous Read on page 50
. Any input on
CLK is ignored while in Asynchronous mode.
