Cypress S29GL01GP, Руководство пользователя

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Document Number: 002-00886 Rev. *B Page 62 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
11.7.5 Erase And Programming Performance
N
otes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V V
CC
, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, V
CC
= 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 32-word write buffer operation.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables –.
11.7.6 TSOP Pin and BGA Package Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 100 MHz.
Erase And Programming Performance
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit Comments
Sector Erase Time 0.5 3.5 sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
S29GL128P 64 256
sec
S29GL256P 128 512
S29GL512P 256 1024
S29GL01GP 512 2048
Total Write Buffer Time (Note 3) 480 µs
Excludes system level
overhead (Note 5)
Total Accelerated Write Buffer Programming Time
(Note 3)
432 µs
Chip Program Time
S29GL128P 123
sec
S29GL256P 246
S29GL512P 492
S29GL01GP 984
Package Capacitance
Parameter Symbol Parameter Description Test Setup Typ Max Unit
C
IN
Input Capacitance V
IN
= 0 6 10 pF
C
OUT
Output Capacitance V
OUT
= 0 10 12 pF
C
IN2
Control Pin Capacitance V
IN
= 0 8 10 pF
WP#/ACC Separated Control Pin V
IN
= 0 42 45 pF
RESET# Separated Control Pin V
IN
= 0 25 28 pF
CE# Separated Control Pin V
IN
= 0 22 25 pF