Cypress S29GL01GP Скачать руководство пользователя страница 35

Страница: 35 / 82

Document Number: 002-00886 Rev. *B

Page 35 of 83

S29GL01GP

S29GL512P
S29GL256P
S29GL128P

Notes
1. DQ5 switches to

when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer

DQ5: Exceeded Timing Limits on page 35

for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation

7.9

Writing Commands/Command Sequences

During a write operation, the system must drive CE# and WE# to V

and OE# to V

when providing an address, command, and

data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An
erase operation can erase one sector, multiple sectors, or the entire device.

Table

–

Table

indicate the address space that each

sector occupies. The device address space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits
required to uniquely select a sector. I

CC2

in “DC Characteristics” represents the active current specification for the write mode. “AC

Characteristics” contains timing specification tables and timing diagrams for write operations.

7.9.1

RY/BY#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

. This feature allows the host system to detect

when data is ready to be read by simply monitoring the RY/BY# pin, which is a dedicated output.

7.9.2

Hardware Reset

The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at
least a period of t

(RESET# Pulse Width), the device immediately terminates any operation in progress, tristates all outputs, resets

the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the
internal state machine to reading array data.

To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the device is ready to accept
another command sequence.

When RESET# is held at V

, the device draws V

reset current (I

CC5

). If RESET# is held at V

, but not at V

, the standby

current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the
Flash memory upon a system reset. See

Figure 11.7 on page 55

and

Figure 11.8 on page 56

for timing diagrams.

Write Operation Status

Status

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3