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Document Number: 002-00948 Rev. *C

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 29. Toggle Bit Timings (During Embedded Algorithms)

Note

73.VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 30. DQ2 vs. DQ6 for Erase/Erase Suspend Operations

Note

74.The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

Figure 31. Synchronous Data Polling Timing/Toggle Bit Timings

Notes

75. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
76. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
77. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.
78. Data polling requires burst access time delay.

WE#

CE#

OE#

High Z

t

OE

DQ6/DQ2

RY/BY#

t

BUSY

Addresses

VA

t

OEH

t

CE

t

CH

t

OH

t

DF

VA

VA

t

ACC

t

RC

Valid Data

Valid Status

Valid Status

(first read)

(second read)

(stops toggling)

Valid Status

VA

WE#

DQ6

DQ2

Enter Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase Suspend

Program

Erase Suspend

Read

Erase

Erase

Complete

CE#

CLK

ADV#

Addresses

OE#

Data

RDY

Status Data

Status Data

V A

V A

t

OE

t

OE

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Содержание S29CD016J

Страница 1: ...bottom Flexible Sector Architecture CD016J and CL016J Eight 2k Double word Thirty 16k Double word and Eight 2k Double Word sectors CD032J and CL032J Eight 2k Double word Sixty two 16k Double Word and...

Страница 2: ...CL032J_Recommend_AN for programming best practices Read Access Times Speed Option MHz 75 32 Mb only 66 56 40 Max Asynch Access Time ns tACC 54 54 54 54 Max Synch Burst Access ns tBACC 8 8 8 8 Min Init...

Страница 3: ...39 8 3 Persistent Protection Bit Lock Bit 41 8 4 Dynamic Protection Bits 41 8 5 Password Protection Method 42 8 6 Hardware Data Protection Methods 43 9 Secured Silicon Sector Flash Memory Region 44 9...

Страница 4: ...Autoselect ID 1 7E 36 01 00 Autoselect ID S29CD016J only 0 7E 46 01 00 Autoselect ID S29CL016J only 0 7E 09 01 00 Autoselect ID S29CD032J only 0 7E 49 01 00 Autoselect ID S29CL032J only Temperature Ra...

Страница 5: ...BGA packages omits the leading S29 2 Contact factory for availability S29CD J CL J Valid Combinations Device Number Initial Burst Access Delay Clock Frequency Package Type Material Set Temperature Ran...

Страница 6: ...output and open drain which require a external pull up resistor When RY BY VOH the device is ready to accept read operations and commands When RY BY VOL the device is either executing an embedded algo...

Страница 7: ...r 16 Mb device Data bus is D31 DQ0 IND WAIT Input Output Buffers X Decoder Y Decoder Chip Enable Output Enable Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Re...

Страница 8: ...Write Circuit VCC VSS Upper Bank Address RESET WE CE ADV STATE CONTROL COMMAND REGISTER Upper Bank X Decoder Y Decoder Latches and Control Logic OE DQmax DQ0 DQmax DQ0 Lower Bank Y Decoder X Decoder L...

Страница 9: ...22 23 24 DQ16 DQ17 DQ18 DQ19 VIO VSS DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VIO VSS DQ28 DQ29 DQ30 DQ31 NC A0 A1 A2 DQ15 DQ14 DQ13 DQ12 VSS VIO DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSS VIO DQ3 DQ2 DQ1...

Страница 10: ...LUD MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 mm PER SIDE DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE A 4 DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION 5 CONTROLLI...

Страница 11: ...is exposed to temperatures above 150 C for prolonged periods of time B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 DQ20...

Страница 12: ...ER JESD 95 1 SPP 010 EXCEPT AS NOTED 4 e REPRESENTS THE SOLDER BALL GRID PITCH 5 SYMBOL MD IS THE BALL ROW MATRIX SIZE IN THE D DIRECTION SYMBOL ME IS THE BALL COLUMN MATRIX SIZE IN THE E DIRECTION N...

Страница 13: ...E ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE 0 000 WHEN THERE...

Страница 14: ...Group x32 Address Range A18 A0 Sector Size KDwords Sector Sector Group x32 Address Range A18 A0 Sector Size KDwords Bank 0 Note 9 SA0 Note 8 SG0 00000h 007FFh 2 Bank 1 Note 9 SA15 SG10 20000h 23FFFh...

Страница 15: ...00800h 00FFFh 2 SA32 64000h 67FFFh 16 SA2 SG2 01000h 017FFh 2 SA33 68000h 6BFFFh 16 SA3 SG3 01800h 01FFFh 2 SA34 6C000h 6FFFFh 16 SA4 SG4 02000h 027FFh 2 SA35 SG15 70000h 73FFFh 16 SA5 SG5 02800h 02FF...

Страница 16: ...7FFFh 16 SA51 SG19 B0000h B3FFFh 16 SA13 18000h 1BFFFh 16 SA52 B4000h B7FFFh 16 SA14 1C000h 1FFFFh 16 SA53 B8000h BBFFFh 16 SA15 SG10 20000h 23FFFh 16 SA54 BC000h BFFFFh 16 SA16 24000h 27FFFh 16 SA55...

Страница 17: ...ditional WP pin sector protection feature SA35 SG15 70000h 73FFFh 16 SA75 SG29 FE800h FEFFFh 2 SA36 74000h 77FFFh 16 SA76 Note 16 SG30 FF000h FF7FFh 2 SA37 78000h 7BFFFh 16 SA77 Note 16 SG31 FF800h FF...

Страница 18: ...50 AC000h AFFFFh 16 SA12 14000h 17FFFh 16 SA51 SG19 B0000h B3FFFh 16 SA13 18000h 1BFFFh 16 SA52 B4000h B7FFFh 16 SA14 1C000h 1FFFFh 16 SA53 B8000h BBFFFh 16 SA15 SG10 20000h 23FFFh 16 SA54 BC000h BFFF...

Страница 19: ...able The device must be set up appropriately for each operation Table 5 describes the required state of each control pin for any particular operation Legend L Logic Low VIL H Logic High VIH X Don t ca...

Страница 20: ...be used for device selection CE must be set to VIL to read data OE is the output control and should be used to gate data to the output pins if the device is selected OE must be set to VIL in order to...

Страница 21: ...nitialization until VCC and VIO have reached their steady state voltages See VCC and VIO Power up on page 52 7 4 Synchronous Burst Read Mode and Configuration Register When a series of adjacent addres...

Страница 22: ...for Bit 6 is 1 indicating that the device delivers data on the rising edge of the CLK signal 24 The device is capable of holding data for one CLK cycle 25 If RESET is asserted low during a burst acce...

Страница 23: ...id clock edge after ADV assertion or the rising edge of ADV until the first valid CLK edge when the data is valid Burst access is initiated and the address is latched on the first rising CLK edge when...

Страница 24: ...Configuration Register commands The Configuration Register is readable at any time however writing the Configuration Register is restricted to times when the Embedded Algorithm is not active If the u...

Страница 25: ...1 Reserved CR8 IND WAIT Configuration WC 0 IND WAIT Asserted During Delay Default 1 IND WAIT Asserted One Data Cycle Before Delay CR7 Burst Sequence BS 0 Reserved 1 Linear Burst Order Default CR6 Clo...

Страница 26: ...codes in system the host system can issue the autoselect command via the command This method does not require VID See Command Definitions on page 67 for details on using the autoselect mode Autoselect...

Страница 27: ...by writing two unlock write cycles followed by the program setup command The program address and data are written next which in turn initiate the Embedded Program algorithm The system is not required...

Страница 28: ...other falling edge of the WE or CE occurs within the 80 s time out window the timer is reset Any command other than Erase Suspend during the time out period will be interpreted as an additional sector...

Страница 29: ...Definitions on page 67 in the appendix shows the address and data requirements for the chip erase command sequence When the Embedded Erase algorithm is complete that bank returns to the read mode and...

Страница 30: ...mine the status of the program operation using the DQ7 DQ6 and or RY BY status bits just as in the standard program operation To resume the sector erase operation the system must write the Erase Resum...

Страница 31: ...ents for the unlock bypass command sequences During the unlock bypass mode only the Read Unlock Bypass Program and Unlock Bypass Reset commands are valid To exit the unlock bypass mode the system must...

Страница 32: ...a polling DQ7 may give misleading status when an attempt is made to program or erase a protected sector During the Embedded Erase Algorithm Data polling produces a 0 on DQ7 When the Embedded Erase alg...

Страница 33: ...DQ2 toggles when the system performs two consecutive reads at addresses within those sectors that have been selected for erasure But DQ2 cannot distinguish whether the sector is actively erasing or is...

Страница 34: ...ctors selected for erasure does not toggle toggles at an address within sectors not selected for erasure returns array data returns array data The system can read from any sector not selected for eras...

Страница 35: ...llowing each sub sequent sector erase command If DQ3 is high on the second status check the last command might not have been accepted Table 13 shows the status of DQ3 relative to the other status bits...

Страница 36: ...de writing the reset command returns the device to the erase suspend read mode However once programming begins the device ignores the reset commands until the operation is complete The reset command m...

Страница 37: ...2 3 64 bit Password One Time Protect 1 PPBs Locked 0 PPBs Unlocked Memory Array Sector Group 0 Sector Group 1 Sector Group 2 Sector Group N 2 Sector Group N 1 Sector Group N 4 PPB 0 PPB 1 PPB 2 PPB N...

Страница 38: ...re that the password is correct when the Password Mode Locking Bit is set as there is no means to verify the password afterwards 2 If both lock bits are selected to be programmed to zeros at the same...

Страница 39: ...times out without programming or erasing the PPB 8 2 1 Programming PPB The PPB Program Command is used to program or set a given PPB The first three cycles in the PPB Program Command are standard unlo...

Страница 40: ...In the event that the erase PPB operation was not successful the user can loop directly to the fourth cycle of the All PPB Erase Command to perform the erase pulse and read verification again After f...

Страница 41: ...asy removal of protection when changes are needed Notes 1 The DYBs can be set or cleared as often as needed with the DYB Write Command 2 When the parts are first shipped the PPBs are cleared the DYBs...

Страница 42: ...of programming 0 s Programming a 1 after a cell is programmed as a 0 results in a time out with the cell as a 0 This is an OTP area 3 The password is all 1 s when shipped from the factory 4 When the p...

Страница 43: ...y write cycles This protects data during VCC power up and power down The command register and all internal program erase circuits are disabled and the device resets to reading array data Subsequent wr...

Страница 44: ...rogram and Sector Erase Resume Issuing the above commands while the Secured Silicon Sector is enabled results in the command being ignored 5 It is valid to execute the Sector Erase command on any sect...

Страница 45: ...9 2 Secured Silicon Sector Entry and Exit Commands The system can access the Secured Silicon Sector region by issuing the three cycle Enter Secured Silicon Sector command sequence The device continues...

Страница 46: ...either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz A new burst operation is required to provide new data ICC8 in DC Characteristic CMOS Compatible on page 49 rep...

Страница 47: ...es above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above tho...

Страница 48: ...vice is guaranteed Table 18 Operating Ranges Parameter Range Ambient Temperature TA Industrial Devices 40 C to 85 C Extended Devices 40 C to 125 C VCC Supply Voltages VCC for 2 6V regulated voltage ra...

Страница 49: ...nchronous Read Current 52 CE VIL OE VIL 1 MHz 10 mA ICC3 VCC Active Program Current 53 54 55 CE VIL OE VIH ACC VIH 40 50 mA ICC4 VCC Active Erase Current 53 54 55 CE VIL OE VIH ACC VIH 20 50 mA ICC5 V...

Страница 50: ...ash Figure 14 ICC1 Current vs Time Showing Active and Automatic Sleep Currents Note 56 Addresses are switching at 1 MHz Figure 15 Typical ICC1 vs Frequency 0 500 1000 1500 2000 2500 3000 3500 4000 0 1...

Страница 51: ...s Unit Output Load 1 TTL gate Output Load Capacitance CL including jig capacitance 30 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0 0V VIO V Input timing measurement reference levels VIO 2 V...

Страница 52: ...23 Asynchronous Read Operations Parameter Description Test Setup Speed Options Unit JEDEC Std 75 MHz 0R 66 MHz 0P 56 MHz 0M 40 MHz 0J 1J tAVAV tRC Read Cycle Time Note 1 Min 54 ns tAVQV tACC Address...

Страница 53: ...cluding the READ RESET command Only a single array access occurs after the F0h command is entered All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Regi...

Страница 54: ...ns tINDH IND WAIT Hold from CLK Note 63 Min 2 2 3 3 ns tIACC CLK to Valid Data Out Initial Burst Access Max 48 54 54 54 ns tCLK CLK Period Min 13 3 15 15 17 85 25 ns Max 60 tCR CLK Rise Time Note 63 M...

Страница 55: ...mand Only a single array access occurs after the F0h command is entered All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register Da Da 2 Da 3 Da 7 OE...

Страница 56: ...or Write See Note Max 11 s tREADY2 RESET Pin Low Not during embedded Algorithms to Read or Write See Note Min 500 ns tRP RESET Pulse Width Min 500 ns tRH RESET High time Before Read See Note Min 50 n...

Страница 57: ...ing Edge Min 18 ns tWHDX tDH Data Hold from WE Rising Edge Min 2 ns tGHWL tWEH Read Recovery Time Before Write OE High to WE Low WE Hold Time Note 67 Min 0 ns tOEP OE Pulse Width Note 67 Min 16 ns tEL...

Страница 58: ...d Address for reading status data see Write Operation Status on page 32 OE WE CE VCC Data Addresses tDS tAH tDH tWP PD tWHWH1 tWC tAS tWPH tVCS 555h PA PA Read Status Data last two cycles A0h tCS Stat...

Страница 59: ...status read cycle and array data read cycle OE CE WE Addresses tOH Data Valid In Valid In Valid PA Valid RA tWC tWPH tAH tWP tDS tDH tRC tCE Valid Out tOE tACC tOEH tGHWL tDF Valid In CE Controlled Wr...

Страница 60: ...ronous data polling Timings Toggle bit Timing 76 VA Valid Address Two read cycles are required to determine status When the Embedded Algorithm operation is complete the toggle bits will stop toggling...

Страница 61: ...ect A 7 0 3Ah Valid address for sector unprotect A 7 0 3Ah Command for sector protect is 68h Command for sector unprotect is 60h Command for sector protect verify is 48h Command for sector unprotect v...

Страница 62: ...Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 35 ns tEHDX tDH Data Hold Time 16 Mb Min 2 ns 32 Mb Min 5 ns tGHEL tGHEL Read Recovery Time Before Write OE High to W...

Страница 63: ...initions 89 PPBs have a program erase cycle endurance of 100 cycles 90 Guaranteed cycles per sector is 100K minimum 17 9 PQFP and Fortified BGA Pin Capacitance Notes 91 Sampled not 100 tested 92 Test...

Страница 64: ...n please refer to the CFI Specification and CFI Publication 100 Contact a Cypress representative for copies of these documents Table 30 CFI Query Identification String Addresses Data Description 10h 1...

Страница 65: ...h 0001h Erase Block Region 2 Information refer to the CFI specification or CFI publication 100 Address 31h data 001Dh 16 Mb device 003Dh 32 Mb device 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Bloc...

Страница 66: ...pported DQ7 DQ4 volt in hex DQ3 DQ0 100 mV in BCD 4Fh 0001h Top Bottom Boot Sector Flag 1 byte 00h Uniform device no WP control 01h 8 x 8 Kb sectors at top and bottom with WP control 02h Bottom boot d...

Страница 67: ...ector for a command WD Write Data See Configuration Register definition for specific write data Data latched on rising edge of WE X Don t care 93 See Table 5 for description of bus operations 94 All v...

Страница 68: ...indicator bit If protected DQ0 1 if unprotected DQ0 0 RD 1 Read Data DQ1 protection indicator bit If protected DQ1 1 if unprotected DQ1 0 SA Sector Address The set of addresses that comprise a sector...

Страница 69: ...e Tables 3 and 4 Advanced Sector Protection Unprotection Added Advanced Sector Protection Unprotection figure Added figures for PPB Erase and Program Algorithm Electronic Marking Added in Electronic M...

Страница 70: ...Suspend Erase Resume Commands Modified second paragraph Replaced allowable operations table with bulleted list Program Suspend Program Resume Commands Replaced allowable operations table with bullete...

Страница 71: ...10th character option descriptions Block Diagram Deleted WORD input 2 4 8 Double Word Linear Burst Operation In 32 Bit Linear and Burst Data Order table deleted reference to WORD input Sector Erase M...

Страница 72: ...r 32 Mb and 16 Mb Corrected values for tBDH with separate values for 16Mb and 32Mb Added tWADVS parameter to table Figure Synchronous Command Write Read Timing Added timing definition for tWADVS Table...

Страница 73: ...cation note links Revision History Corrected heading for May 25 2011 edits from revision B4 to B5 10 11 2012 Valid Combinations Updated Valid Combinations table to add clarity and make explicit which...

Страница 74: ...is the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this information and any resulting product Cypress produc...

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