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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
M8C Microprocessor
2.4
Instruction Formats
The M8C has a total of seven instruction formats which use instruction lengths of one, two, and three
bytes. All instruction bytes are fetched from the program memory (Flash), using an address and data
bus that are independent from the address and data buses used for register and RAM access.
While examples of instructions are given in this section, refer to the
M8C Instruction Set chapter on
for detailed information on individual instructions.
2.4.1
One-Byte Instruction
Many instructions, such as some of the MOV instructions, have single-byte forms, because they do
not use an address or data as an operand. As shown in
, one-byte instructions use an 8-bit
opcode. The set of one-byte instructions can be divided into four categories, according to where their
results are stored.
The first category of one-byte instructions are those that do not update any registers or RAM. Only
the one-byte no operation (NOP) and supervisory system call (SSC) instructions fit this category.
While the program counter is incremented as these instructions execute, they do not cause any
other internal M8C registers to be updated, nor do these instructions directly affect the register
space or the RAM address space. The SSC instruction will cause SROM code to run, which will
modify RAM and the M8C internal registers.
The second category has only the two PUSH instructions in it. The PUSH instructions are unique,
because they are the only one-byte instructions that cause a RAM address to be modified. These
instructions automatically increment the CPU_SP register (
SP
).
The third category has only the HALT instruction in it. The HALT instruction is unique, because it is
the only one-byte instruction that causes a user register to be modified. The HALT instruction modi-
fies user register space address FFh (CPU_SCR register).
The final category for one-byte instructions are those that cause updates of the internal M8C regis-
ters. This category holds the largest number of instructions:
ASL
,
ASR
,
CPL
,
DEC
,
INC
,
MOV
,
POP
,
RET
,
RETI
,
RLC
,
ROMX
,
RRC
,
SWAP
. These instructions can cause the CPU_A, CPU_X, and CPU_SP
registers, or SRAM to update.
2.4.2
Two-Byte Instructions
The majority of M8C instructions are two bytes in length. While these instructions can be divided into
categories identical to the one-byte instructions, this would not provide a useful distinction between
the three two-byte instruction formats that the M8C uses.
Table 2-4. One-Byte Instruction Format
Byte 0
8-Bit Opcode
Table 2-5. Two-Byte Instruction Formats
Byte 0
Byte 1
4-Bit
Opcode
12-Bit Relative Address
8-Bit Opcode
8-Bit Data
8-Bit Opcode
8-Bit Address
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