Cypress PSoC CY8CTMG20 Series, Техническое справочное руководство

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192 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SPI_CR
0,2Bh
21.3.5 SPI_CR
SPI Control Register
This register is the SPI control register.
The LSb First, Clock Phase, and Clock Polarity bits are configuration bits. Do not change them once the block is enabled.
These bits can be set at the same time that the block is enabled. For additional information, refer to the
Register Definitions
on page 147 in the SPI chapter.
7 LSb First Do not change this bit during an SPI transfer.
0
Data is shifted out MSb first.
1 Data is shifted out LSb first.
6 Overrun 0 No overrun has occurred.
1 Overrun has occurred. Indicates that a new byte is received and loaded into the RX Buffer
before the previous one is read. It is cleared on a read of this (CR0) register.
5 SPI Complete 0 Indicates that a byte may still be in the process of shifting out, or no transmission is active.
1 Indicates that a byte is shifted out and all associated clocks are generated. It is cleared on a
read of this (CR0) register. Optional interrupt.
4 TX Reg Empty Reset state and the state when the block is disabled is ‘1’.
0
Indicates that a byte is currently buffered in the TX register.
1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer (DR1)
register. This is the default interrupt. This status is initially asserted on block enable; how-
ever, the TX Reg Empty interrupt occurs only after the first data byte is written and trans-
ferred into the shifter.
3 RX Reg Full 0 RX register is empty.
1 A byte is received and loaded into the RX register. It is cleared on a read of the RX Buffer
(DR2) register.
2 Clock Phase 0 Data is latched on the leading clock edge. Data changes on the trailing edge (modes 0, 1).
1 Data changes on the leading clock edge. Data is latched on the trailing edge (modes 2, 3).
1 Clock Polarity 0 Non-inverted, clock idles low (modes 0, 2).
1 Inverted, clock idles high (modes 1, 3).
0 Enable 0 SPI function is not enabled.
1 SPI function is enabled.
Individual Register Names and Addresses:
0,2Bh
SPI_CR : 0,2Bh
7 6 5 4 3 2 1 0
Access : POR RW : 0 R : 0 R : 0 R : 1 R : 0 RW : 0 RW : 0 RW : 0
Bit Name LSb First Overrun SPI Complete TX Reg Empty RX Reg Full Clock Phase Clock Polarity Enable
Bit Name Description
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