Document # 001-20559 Rev. *D
209
Digital Blocks
17.3.8
Transmitter Timing
Enable/Disable Operation.
As soon as the block is config-
ured for the transmitter and before enabling, the primary
output is set to idle at logic 1, the mark state. The output
remains '1' until the block is enabled and a transmission is
initiated. The auxiliary output also idles to '1', which is the
idle state of the associated SPI mode 3 clock.
When the transmitter is enabled, the internal reset is
released on the divide-by-eight clock generator circuit. On
the next positive edge of the selected input clock, this 3-bit
up counter circuit, which generates the bit clock with the
MSb, starts counting up from 00h, and is free running there-
after.
When the block is disabled, the clock is immediately gated
low. All internal states are reset (including CR0 status) to
their configuration-specific reset state, except for DR0, DR1,
and DR2, which are unaffected.
Transmit Operation.
Transmission is initiated with a write
to the TX Buffer register (DR1). The CPU write to this regis-
ter is required to have one-half bit clock set up time for the
data, to be recognized at the next positive internal bit clock
edge. As shown in
, once the set up time is
met, there is one clock of latency until the data is loaded into
the shifter and the START bit is generated to the TXD (pri-
mary) output.
Figure 17-24. Typical Transmitter Timing
INTERNAL CLOCK
TX REG EMPTY
START
TXD (F1)
D0
D4
D5
D6
D7
Free running
clock is CLK
input divided
by eight.
User writes
first byte to the
TX Buffer
register.
Shifter is loaded
with the first byte.
User writes next
byte to the TX
Buffer register.
SCLK (F2)
Shifter is loaded with
the next byte.
STOP
PAR
TX Buffer write needs one-half cycle set
up time to the internal clock.
One cycle of latency before
START bit at the TXD output.
START
Содержание PSoC CY8C23533
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