Document Number: 002-xxxxx Rev. **
Page 18 of 42
PRELIMINARY
CYBLE-013025-00
CYBLE-013030-00
Serial Peripheral Interface
The CYBLE-0130XX-00 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or
a slave. Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYBLE-0130XX-00 has optional I/O ports that can be configured individually and separately for each functional pin as shown in
, and
. The CYBLE-0130XX-00 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The
CYBLE-0130XX-00 can also act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Microprocessor Unit
The CYBLE-0130XX-00 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer
components. The microprocessor is based on an ARM
®
Cortex
®
M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG
interface units. The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM
code. The SoC has a total storage of 380 KB, including RAM and ROM.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with
an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed
from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
Table 9. CYBLE-0130XX-00 First SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
1
1. SPIFFY1 MISO should always be P32. Boot ROM does not configure any others.
SPI_CS
2
2. Any GPIO can be used as SPI_CS when SPI 1 is in master mode, and when the SPI slave is not a serial flash.
Configured Pin Name
SCL
SDA
–
–
–
–
–
–
–
–
P32
P33
3
3. P33 is always SPI_CS when a serial flash is used for non-volatile storage.
Table 10. CYBLE-0130XX-00 Second SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
1
1. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name
P3
P0
P1
–
–
P4
P25
–
P24
P27
–
–
Table 11. CYBLE-0130XX-00 Second SPI Set (Slave Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
Configured Pin Name
P3
P0
P1
P2
–
P27
–
–
P24
P33
P25
P26
–
–
–
P32
