
Hardware
CYW943907AEVAL1F Evaluation Kit User Guide, Doc. No. 002-18703 Rev. *B
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Figure 4-6. Micro SD Connector Circuit Diagram
4.6 JTAG Connector
4.6.1 Onboard Programmer/Debugger and Serial Interface Chip
The onboard programmer/debugger chip uses JTAG to program/debug the CYW43907-based SiP module.
shows the connection between CYW43907 and the onboard programmer/debugger chip. In addition to the
connections listed in the table, JTAG_SEL and GPIO_8_TAP_SEL lines have been pulled HIGH to make sure
programming/debugging is enabled through JTAG in CYW43907.
Table 4-6. Connection between CYW43907 and Onboard Programmer/Debugger
Sl. No.
CYW43907-Based SIP Pin Name
Onboard Programmer/Debugger Connection
1
GPIO_2_JTAG_TCK
FTDI_JTAG_TCK
2
GPIO_3_JTAG_TMS
FTDI_JTAG_TMS
3
GPIO_4_JTAG_TDI
FTDI_JTAG_TDI
4
GPIO_5_JTAG_TDO
FTDI_JTAG_TDO
5
GPIO_6_JTAG_TRST_L
FTDI_JTAG_TRST
4.7 Connectors
4.7.1 WICED Header
J6 is the WICED header available on the CYW943907AEVAL1F EVK. This is a 44-pin header containing I
2
C, SDIO, UART,
SPI, PWM lines, and I/Os. Note that some signals are shared with the Arduino header (UART0 Tx/Rx) and Onboard
Programmer/debugger chip (UART1).
Table 4-7. WICED Header Pinout
EVAL BOARD HEADER
CYW43907 PIN NAME
SDK ENUMERATION
ALTERNATE ENUMERATION
J6.1
PWM_4
WICED_GPIO_17
WICED_PWM_5
J6.2
PWM_5
WICED_GPIO_18
WICED_BUTTON1
J6.3
I2S0_MCK
WICED_GPIO_28
WICED_I2S_1
J6.4
I2S0_SD_OUT
WICED_GPIO_32
WICED_I2S_1
J6.5
I2S0_SCK_BCLK
WICED_GPIO_29
WICED_I2S_1
J6.6
I2S0_WS_LRCLK
WICED_GPIO_30
WICED_I2S_1