CY8CPROTO-064B0S3 PSoC 64 "Secure Boot" Prototyping Kit Guide, Doc. # 002-29505 Rev. *B
15
3.
Kit Operation
This chapter introduces you to various features of the CY8CPROTO-064B0S3 PSoC 64 “Secure
Boot” Prototyping Kit, including the theory of operation and the onboard KitProg3 programming and
debugging functionality, USB-UART and USB-I2C bridges.
3.1
Theory of Operation
The CY8CPROTO-064B0S3 PSoC 64 “Secure Boot” Prototyping Kit is built around the PSoC 64
chip.
shows the block diagram of the PSoC 64 device. For details of device features, see
the
.
Figure 3-1. PSoC 64 Block Diagram
System
Hibernate Mode
Backup
Domain
System
DeepSleep Mode
System LP/ULP Mode
CPUs Active/Sleep
Color Key:
Power Modes and Domains
CPU Subsystem
SCB
Programmable Analog
SAR ADC 12 bit
SA
R
M
U
X
Temperature Sensor
DS
I
I/
O
Subs
ys
te
m:
U
p
to
5
3
G
P
IO
s,
6
8-
QF
N
P
a
ck
a
ge
B
o
un
da
ry
S
ca
n
2x
S
m
ar
t I
/O
P
o
rt
s
USB
PHY
Sy
st
em
In
ter
co
n
nec
t
(M
u
lti
L
ay
er
A
H
B
, I
P
C
, M
P
U
/S
M
P
U
)
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
3x DMA
Controller
Crypto
DES/TDES, AES, SHA, CRC,
TRNG, RSA/ECC
Accelerator
Flash
512 KB + 32 KB + 32 KB
8 KB cache for each CPU
SRAM
256 KB
ROM
64 KB
P
er
ip
h
er
al
In
ter
co
n
n
ec
t
(M
M
IO
, P
P
U
)
P
er
ip
h
e
ra
l
cl
o
ck
(P
C
LK
)
System Resources
Power
Clocks
POR
LVD
BOD
OVP
Buck Regulator
WCO
RTC
IMO
WDT
2x PLL
ECO
ILO
FLL
2x MCWDT
Backup Regs
XRES Reset
PMIC Control
PSoC 64 “Secure Boot” MCU
CYB06445LQI-S3D42
