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CY62167DV18 MoBL

Document #: 38-05326 Rev. *C

Page 7 of 11

Write Cycle 1

(WE Controlled)

[13, 17, 18]

Write Cycle 2

(CE

or CE

Controlled)

[13, 17, 18]

Switching Waveforms

(continued)

PWE

SCE

HZOE

VALID DATA

NOTE 19

ADDRESS

DATA IO

BHE/BLE

PWE

SCE

HZOE

VALID DATA

NOTE 19

ADDRESS

DATA IO

BHE/BLE

Notes

17. Data IO is high impedance if OE = V

18. If CE

goes HIGH and CE

goes LOW simultaneously with WE = V

, the output remains in a high impedance state.

19. During this period, the IOs are in output state. Do not apply input signals.

[+] Feedback

Содержание CY62167DV18

Страница 1: ...IO0 through IO15 are placed in a high impedance state when Deselected CE1 HIGH or CE2 LOW Outputs are disabled OE HIGH Both Byte High Enable BHE and Byte Low Enable BLE are disabled BHE BLE HIGH Write operation is active CE1 LOW CE2 HIGH and WE LOW To write to the device take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW If BLE is LOW then data from IO pins IO0 through IO7 is wri...

Страница 2: ...guration 3 Notes 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at VCC VCC typ TA 25 C 3 DNU pins must be left floating or tied to VSS to ensure proper operation WE A11 A10 A6 A0 A3 CE1 IO10 IO8 IO9 A4 A5 IO11 IO13 IO12 IO14 IO15 VSS A9 A8 OE A7 IO0 BHE CE2 A17 A2 A1 BLE IO2 IO1 IO3 IO4 IO5 IO6 IO7 A15 A14 A13 A12 A19 A18 DNU 3 2 6 5 4...

Страница 3: ... 0 2 V VIH Input HIGH Voltage 1 4 VCC 0 2 V VIL Input LOW Voltage 0 2 0 4 V IIX Input Leakage Current GND VI VCC 1 1 µA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 µA ICC VCC Operating Supply Current f fMAX 1 tRC VCC 1 95V IOUT 0 mA CMOS level 15 30 mA f 1 MHz 1 5 5 ISB1 Automatic CE Power down Current CMOS Inputs CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V VIN 0 2V f fMAX Address and Data On...

Страница 4: ...R2 10800 Ω RTH 6000 Ω VTH 0 80 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 2 Max Unit VDR VCC for Data Retention 1 0 1 95 V ICCDR Data Retention Current VCC 1 0V CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V or VIN 0 2V 10 µA tCDR 7 Chip Deselect to Data Retention Time 0 ns tR 8 Operation Recovery Time tRC ns Data Retention Waveform 9 VCC min VCC min tCD...

Страница 5: ...s tPWE WE Pulse Width 40 ns tBW BLE BHE LOW to Write End 45 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High 11 12 20 ns tLZWE WE HIGH to Low Z 11 10 ns Notes 10 Test conditions for all parameters other than tri state parameters assume signal transition time of 1 ns V timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loadi...

Страница 6: ... ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tPD tHZBE tLZBE tHZCE tDBE OE CE1 ADDRESS CE2 BHE BLE DATA OUT VCC SUPPLY CURRENT HIGH ICC ISB IMPEDANCE Notes 14 The device is continuously selected OE CE1 VIL BHE and or BLE VIL and CE2 VIH 15 WE is HIGH for read cycle 16 Address valid before or similar to CE1 BHE BLE transition LOW and CE2 transition HIGH Feed...

Страница 7: ...OE VALID DATA tBW NOTE 19 CE1 ADDRESS CE2 WE DATA IO OE BHE BLE tHD tSD tPWE tHA tAW tSCE tWC tHZOE VALID DATA tBW tSA NOTE 19 CE1 ADDRESS CE2 WE DATA IO OE BHE BLE Notes 17 Data IO is high impedance if OE VIH 18 If CE1 goes HIGH and CE2 goes LOW simultaneously with WE VIH the output remains in a high impedance state 19 During this period the IOs are in output state Do not apply input signals Feed...

Страница 8: ... LOW 18 Write Cycle 4 BHE BLE Controlled OE LOW 18 Switching Waveforms continued VALID DATA tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 19 CE1 ADDRESS CE2 WE DATA IO BHE BLE tHD tSD tSA tHA tAW tWC VALID DATA tBW tSCE tPWE NOTE 19 CE1 ADDRESS CE2 WE DATA IO BHE BLE Feedback ...

Страница 9: ...Active ICC L H H L L H Data Out IO8 IO15 High Z IO0 IO7 Read Active ICC L H L X L L Data In IO0 IO15 Write Active ICC L H L X H L High Z IO8 IO15 Data In IO0 IO7 Write Active ICC L H L X L H Data In IO8 IO15 High Z IO0 IO7 Write Active ICC L H H H L H High Z Output Disabled Active ICC L H H H H L High Z Output Disabled Active ICC L H H H L L High Z Output Disabled Active ICC Ordering Information S...

Страница 10: ...port systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Package Diagrams Figure 1 48 Ball VFBGA 8 x 9 5 x 1 mm 51 85178 MoBL is a registered trademark and M...

Страница 11: ...te Orig of Change Description of Change 118406 09 30 02 GUG New Data Sheet A 123690 02 11 03 DPM Changed Advance to Preliminary Added package diagram B 126554 04 25 03 DPM Minor Change Changed sunset owner from DPM to HRT C 1015643 See ECN VKN Converted from preliminary to final Removed L parts Removed 70 ns speed bin Updated footnote 3 Updated Ordering Information table Feedback ...

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