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CY62146DV30

Document #: 38-05339 Rev. *A

Page 10 of 11

© Cypress Semiconductor Corporation, 2005. The information contained herein is subject  to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

 

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company

names mentioned in this document may be the trademarks of their respective holders.

Package Diagram

48-Lead VFBGA (6 x 8 x 1 mm) BV48A

51-85150-*B

44-Pin TSOP II ZS44

51-85087-*A

[+] Feedback 

Содержание CY62146DV30

Страница 1: ... CE HIGH outputs are disabled OE HIGH both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH or during a write operation CE LOW and WE LOW Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from I O pins I O0 through I O7 is written into the location specified on the address pins A0 through A17 If Byte ...

Страница 2: ...E NC A17 A2 A1 BLE VCC I O2 I O1 I O3 I O4 I O5 I O6 I O7 A15 A14 A13 A12 NC NC NC 3 2 6 5 4 1 D E B A C F G H A16 DNU Vcc WE 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 VCC A17 A16 A15 A14 A4 A3 OE VSS A5 I O15 A2 CE I O2 I O0 I O1 BHE A1 A0 18 17 20 19 I O3 27 28 25 26 22 21 23 24 VSS I O6 I O4 I O5 I O7 A6 A7 BLE VCC I O14 I O13 I O12 I O11 I O10 I O9 ...

Страница 3: ... Output LOW Voltage IOL 0 1 mA VCC 2 20V 0 4 0 4 0 4 V IOL 2 1 mA VCC 2 70V 0 4 0 4 0 4 V VIH Input HIGH Voltage VCC 2 2V to 2 7V 1 8 VCC 0 3V 1 8 VCC 0 3V 1 8 VCC 0 3V V VCC 2 7V to 3 6V 2 2 VCC 0 3V 2 2 VCC 0 3V 2 2 VCC 0 3V V VIL Input LOW Voltage VCC 2 2V to 2 7V 0 3 0 6 0 3 0 6 0 3 0 6 V VCC 2 7V to 3 6V 0 3 0 8 0 3 0 8 0 3 0 8 V IIX InputLeakage Current GND VI VCC 1 1 1 1 1 1 µA IOZ Output L...

Страница 4: ...ics Over the Operating Range Parameter Description Conditions Min Typ 5 Max Unit VDR VCC for Data Retention 1 5 V ICCDR Data Retention Current VCC 1 5V CE VCC 0 2V VIN VCC 0 2V or VIN 0 2V L 9 µA LL 6 tCDR 9 Chip Deselect to Data Retention Time 0 ns tR 11 Operation Recovery Time tRC ns VCC VCC OUTPUT R2 50 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 Rise Time 1 V ns Fall Time 1 V ns OUTPUT V Equiva...

Страница 5: ...0 0 ns tPWE WE Pulse Width 35 40 45 ns tBW BLE BHE LOW to Write End 40 40 60 ns tSD Data Set up to Write End 25 25 30 ns tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High Z 13 14 15 20 25 ns tLZWE WE HIGH to Low Z 13 10 10 10 ns Notes 12 Test conditions for all parameters other than three state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of VCC t...

Страница 6: ...ously selected OE CE VIL BHE and or BLE VIL 17 WE is HIGH for read cycle 18 Address valid prior to or coincident with CE and BHE BLE transition LOW ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID tRC tAA tOHA 50 50 DATA VALID tRC tACE tLZBE tLZCE tPU DATA OUT HIGH IMPEDANCE IMPEDANCE ICC ISB tHZOE tHZCE tPD OE CE HIGH VCC SUPPLY CURRENT tHZBE BHE BLE tLZOE ADDRESS tDBE tDOE Feedback ...

Страница 7: ...IGH simultaneously with WE VIH the output remains in a high impedance state 21 During this period the I Os are in output state and input signals should not be applied Switching Waveforms continued tHD tSD tPWE tSA tHA tAW tWC DATA I O ADDRESS CE WE OE tHZOE DATAIN NOTE 21 BHE BLE tBW tSCE tHD tSD tPWE tHA tAW tSCE tWC tHZOE DATAIN CE ADDRESS WE DATA I O OE NOTE 21 BHE BLE tBW tSA Feedback ...

Страница 8: ... LOW 20 Write Cycle No 4 BHE BLE Controlled OE LOW 20 Switching Waveforms continued DATAIN tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE CE ADDRESS WE DATAI O NOTE 21 tBW BHE BLE DATA I O ADDRESS tSD tSA tHA tAW tWC CE WE DATAIN NOTE 21 tBW BHE BLE tSCE tPWE tHZWE tHD tLZWE Feedback ...

Страница 9: ...Type Operating Range 45 CY62146DV30LL 45BVI BV48A 48 ball Very Fine Pitch BGA 6 mm 8mm 1 mm Industrial CY62146DV30LL 45BVXI 48 ball Very Fine Pitch BGA 6 mm 8mm 1 mm Pb free CY62146DV30LL 45ZSXI ZS 44 44 pin TSOP II Pb free 55 CY62146DV30L 55BVI BV48A 48 ball Very Fine Pitch BGA 6 mm 8mm 1 mm Industrial CY62146DV30L 55BVXI 48 ball Very Fine Pitch BGA 6 mm 8mm 1 mm Pb free CY62146DV30LL 55BVI 48 ba...

Страница 10: ...ress written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifie...

Страница 11: ...O Issue Date Orig of Change Description of Change 213251 See ECN AJU New Data Sheet A 316039 See ECN PCI Added 45 ns Speed Bin in AC DC and Ordering Information tables Added Footnote 10 on page 4 Added Pb free package ordering information on page 9 Changed 44 lead TSOP II package name on page 10 from Z44 to ZS44 Standardized Icc values across L and LL bins Feedback ...

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