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PRELIMINARY

CY14B101Q1
CY14B101Q2
CY14B101Q3

Document #: 001-50091 Rev. *A

Page 9 of 22

Write Protection and Block Protection

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features

for both software and hardware write protection using WRDI

instruction and WP. Additionally, this device also provides block

protection mechanism through BP0 and BP1 pins of the Status

WEN bit of the status register. The write instructions (WRSR and

WRITE) and nvSRAM special instruction (STORE, RECALL,

ASENB, and ASDISB) need the write to be enabled (WEN bit =

1) before they can be issued.

Write Enable (WREN) Instruction

On power up, the device is always in the write disable state. The

following WRITE, WRSR, or nvSRAM special instruction must

therefore be preceded by a Write Enable instruction. If the device

is not write enabled (WEN = ‘0’), it ignores the write instructions

and returns to the standby state when CS is brought HIGH. A

new CS falling edge is required to re-initiate serial communi-

cation. The instruction is issued following the falling edge of CS.

When this instruction is used, the WEN bit of status register is

set to ‘1’. WEN bit defaults to ‘0’ on power up.

Note

After completion of a write instruction (WRSR or WRITE)

or nvSRAM special instruction (STORE, RECALL, ASENB, and

ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to

provide protection from any inadvertent writes. Therefore,

WREN instruction needs to be used before a new write

instruction is issued.

Write Disable (WRDI) Instruction

Write Disable instruction disables the write by clearing the WEN

bit to ‘0’ in order to protect the device against inadvertent writes.

This instruction is issued following falling edge of CS followed by

opcode for WRDI instruction. The WEN bit is cleared on the

rising edge of CS following a WRDI instruction.

Block Protection

Block protection is provided using the BP0 and BP1 pins of the

Status register. These bits can be set using WRSR instruction

and probed using the RDSR instruction. The nvSRAM is divided

into four array segments. One-quarter, one-half, or all of the

memory segments can be protected. Any data within the

protected

segment is read only.

Table 6

shows the function of

Block Protect bits.

Figure 8. Write Status Register (WRSR) Instruction Timing

SCK

0 1 2 3

4 5 6 7

0 0 0 0 0 0 0 1

MSB

LSB

HI-Z

0 1 2 3 4 5

6 7

Opcode

Data in

Figure 9. WREN Instruction

0 0

0 1

SCK

Hi-Z

0 1 2 3

4 5

6 7

Figure 10. WRDI Instruction

Table 6. Block Write Protect Bits

Level

Status Register

Bits

Array Addresses Protected

BP1

BP0

None

1 (1/4)

0x18000-0x1FFFF

2 (1/2)

0x10000-0x1FFFF

3 (All)

0x00000-0x1FFFF

SCK

Hi-Z

0 1 2 3

4 5

6 7

[+] Feedback

Содержание CY14B101Q1

Страница 1: ...t of 10 mA at 40 MHz operation Industry Standard Configurations Commercial and industrial temperatures CY14B101Q1 has identical pin configuration to industry stan dard 8 pin NV Memory 8 pin DFN and 16 pin SOIC Packages RoHS compliant Functional Overview The Cypress CY14B101Q1 CY14B101Q2 CY14B101Q3 combines a 1 Mbit nonvolatile static RAM with a nonvolatile element in each memory cell The memory is...

Страница 2: ...ternal pull up keeps this pin pulled high If not used this pin is left as No Connect Output Indicates busy status of nvSRAM when LOW Input Hardware STORE implemented by pulling this pin LOW externally VCAP Power Supply AutoStore Capacitor Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements If AutoStore is not needed this pin must be left as No Connect...

Страница 3: ...ser to perform infinite write operations A Write cycle is performed through the SPI WRITE instruction The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode three bytes of address and one byte of data Write to nvSRAM is done at SPI bus speed with zero cycle delay The device allows burst mode writes to be performed through SPI This enables write operations...

Страница 4: ...uration or as long as HSB pin is LOW The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when a STORE cycle initiated by any means or Power up RECALL is in progress Upon completion of the STORE operation the nvSRAM remains disabled until the HSB pin returns HIGH Leave the HSB pin unconnected if not used Note CY14B101Q1 CY14B101Q2 do not have HSB...

Страница 5: ...CS For selecting any slave device the master needs to pull down the corresponding CS pin Any instruction can be issued to a slave device only while the CS pin is LOW When the device is not selected data through the SI pin is ignored and the serial output pin SO remains in a high impedance state Note A new instruction must begin with the falling edge of Chip Select CS Therefore only one opcode can ...

Страница 6: ...n in Figure 5 and Figure 6 The status of clock when the bus master is in Standby mode and not transferring data is SCK remains at 0 for Mode 0 SCK remains at 1 for Mode 3 CPOL and CPHA bits must be set in the SPI controller for either Mode 0 or Mode 3 The device detects the SPI mode from the status of SCK pin when the device is selected by bringing the CS pin LOW If SCK pin is LOW when device is s...

Страница 7: ...accesses are inhibited and a conditional AutoStore operation is performed AutoStore is not performed if no writes have happened since last RECALL cycle This feature prevents inadvertent writes to nvSRAM from happening during power down However to completely avoid the possibility of inadvertent writes during power down ensure that the device is deselected and is in Standby Power Mode and the Chip S...

Страница 8: ...g the WREN instruction before it is issued The instruction is issued after the falling edge of CS using the opcode for WRSR followed by 8 bits of data to be stored in the Status Register Since only bits 2 3 and 7 can be modified by WRSR instruction it is recommended to leave the other bits as 0 while writing to the Status Register Note In CY14B101Q1 CY14B101Q2 CY14B101Q3 the values written to Stat...

Страница 9: ...ecial instruction STORE RECALL ASENB and ASDISB instruction WEN bit is cleared to 0 This is done to provide protection from any inadvertent writes Therefore WREN instruction needs to be used before a new write instruction is issued Write Disable WRDI Instruction Write Disable instruction disables the write by clearing the WEN bit to 0 in order to protect the device against inadvertent writes This ...

Страница 10: ...er the last address bit is ignored CY14B101Q1 CY14B101Q2 CY14B101Q3 allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction If only one byte is to be read the CS line must be driven HIGH after one byte of data comes out However the read sequence may be continued by holding the CS line LOW and the address is automatic...

Страница 11: ...ng Figure 14 Burst Mode Write Instruction Timing CS SCK SO LSB SI Op Code 17 bit Address MSB LSB 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 20 21 22 23 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 7 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 A16 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 Data Byte 1 Data Byte N MSB LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 D0 D7 CS SCK SO 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 20 21 22 23 0 1 2 3 4 5 6 7 MSB LSB Data D0 D...

Страница 12: ...the positive edge of CS following the ASENB instruction Note If ASDISB and ASENB instructions are executed in CY14B101Q1 the device is busy for the duration of software sequence processing time tSS However ASDISB and ASENB instructions have no effect on CY14B101Q1 as AutoStore is internally disabled HOLD Pin Operation The HOLD pin is used to pause the serial communication When the device is select...

Страница 13: ...7V to 3 6V Industrial 40 C to 85 C 2 7V to 3 6V DC Electrical Characteristics Over the Operating Range VCC 2 7V to 3 6V Parameter Description Test Conditions Min Max Unit ICC1 Average Vcc Current At fSCK 40 MHz 10 mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VC...

Страница 14: ...Test Conditions Max Unit CIN Input Capacitance TA 25 C f 1MHz VCC 3 0V 6 pF COUT Output Pin Capacitance 8 pF Thermal Resistance Parameter 6 Description Test Conditions 8 SOIC 8 DFN Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W ...

Страница 15: ...S CS Setup Time 10 ns tCSH tCEH CS Hold Time 10 ns tSD tSU Data In Setup Time 5 ns tHD tH Data In Hold Time 5 ns tHH tHD HOLD Hold Time 5 ns tSH tCD HOLD Setup Time 5 ns tCO tV Output Valid 9 ns tHHZ tHZ HOLD to Output High Z 15 ns tHLZ tLZ HOLD to Output Low Z 15 ns tOH tHO Output Hold Time 0 ns tHZCS tDIS Output Disable Time 25 ns Figure 21 Synchronous Data Timing Mode 0 Figure 22 HOLD Timing HI...

Страница 16: ...tHHHD tDELAY tDELAY VVCCRISE Note8 Note8 Note11 tLZHSB tLZHSB tFA tFA VSWITCH VHDIS HSB OUT Autostore POWER UP RECALL Read and Write Inhibited RWI POWER UP RECALL POWER UP RECALL Read and Write Read and Write BROWN OUT AUTOSTORE POWER DOWN AUTOSTORE Notes 7 tFA starts from the time VCC rises above VSWITCH 8 If an SRAM write has not taken place since the last nonvolatile cycle AutoStore or Hardware...

Страница 17: ...e 24 Software STORE Cycle 12 Figure 25 Software RECALL Cycle 12 0 0 1 1 1 1 0 0 CS SCK SI RWI Hi Z 0 1 2 3 4 5 6 7 RDY tSTORE 0 1 1 0 0 0 0 0 CS SCK SI 0 1 2 3 4 5 6 7 RWI Hi Z RDY tRECALL Notes 12 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 13 Commands such as STORE and RECALL lock out IO until operation ...

Страница 18: ...ite latch not set 25 ns tPHSB Hardware STORE Pulse Width 15 ns Switching Waveforms Figure 26 Hardware STORE Cycle 8 HSB IN HSB OUT SO RWI HSB IN HSB OUT RWI tHHHD tSTORE tPHSB tDELAY tLZHSB tDELAY tDHSB tDHSB tPHSB HSB pin is driven high to VCC only by Internal 100K resistor HSB driver is disabled SRAM is disabled as long as HSB IN is driven LOW Write Latch not set Write Latch set Feedback ...

Страница 19: ...l CY14B101Q2 LHXC 001 50671 8 DFN with VCAP CY14B101Q3 SFXIT 51 85022 16 SOIC Industrial CY14B101Q3 SFXI 51 85022 16 SOIC CY14B101Q3 SFXCT 51 85022 16 SOIC Commercial CY14B101Q3 SFXC 51 85022 16 SOIC All the above parts are Pb free The above table contains advance information Contact your local Cypress sales representative for availability of these parts Part Numbering Nomenclature Option T Tape R...

Страница 20: ...1Q3 Document 001 50091 Rev A Page 20 of 22 Package Diagrams Figure 27 8 Pin 300 mil DFN Package 001 50671 1 ALL DIMENSIONS ARE IN MILLIMETERS 3 BASED ON REF JEDEC MO 240 EXCEPT DIMENSIONS L and b NOTES 2 PACKAGE WEIGHT TBD 001 50671 A Feedback ...

Страница 21: ...PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document 001 50091 Rev A Page 21 of 22 Figure 28 16 Pin 300 mil SOIC 51 85022 Package Diagrams continued 51 85022 B Feedback ...

Страница 22: ...nges without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypre...

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