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Design Considerations
AN64846 - Getting Started with CapSense
®
Doc. No. 001-64846 Rev. *X
88
3.8.15 CapSense System Design with Single Layer PCB
Electronic product manufacturers face constant pressure to lower system costs. Several markets, including consumer
and home appliances, are switching to single layer PCBs to support their required prod
uct margins. Cypress’s
CapSense controllers provide robust touch sensing on single layer PCBs, and their driven shield capability enables
longer trace length, proximity sensing, and liquid tolerance. CapSense delivers IEC (IEC 61000-6-1, IEC 61000-6-2)
noise compliant performance for accurate touch responses even in noisy environments using sophisticated firmware
algorithms. For more details on implementing CapSense touch sensing on single layer boards, contact
Schematic and Layout Checklist
before you start your design to ensure that the best practices for a CapSense
design are followed.
3.8.16 CapSense System Design with ITO
For applications where the CapSense sensors need to be transparent (sensors are positioned over the display),
CapSense sensors can be implemented with ITO. However, if transparent sensors are not required, it is recommended
to use copper pads as it provides a higher yield, lower cost, and better performance when compared to ITO sensors.
The ITO sensors can be implemented on a glass substrate or a plastic film (polyethylene terephthalate) substrate. The
sensor shape recommended in section
for button sensors and section
applies to the sensor design on ITO. Make sure that the sensor length or width (where length is the always the longest
dimension) aspect ratio does not exceed 5/3.
Trace length for the sensors should be kept at minimum to reduce the overall sensor resistance. The formula for trace
resistance is provided in the following equation:
Resistance = Trace sheet resistance × Trace length ÷ Trace width
Trace resistance is evaluated relative to the sensor resistance. High trace resistance, compared to the sensor
resistance, degrades the touch performance. Therefore, it is recommended to keep the sensor trace length as short as
possible. The layout guidelines for ITO sensors are summarized in
Table 3-10. Layout Guidelines for ITO Sensors
Category
Parameter
Min
Typ
Max
Units
Remarks
ITO
Sheet Resistance (Glass
Substrate)
-
-
120
Ω/sq
-
Sheet Resistance (Film
Substrate)
-
-
270
Ω/sq
-
Sensor Max Resistance
-
1
30
k
Ω
End-to-end
Spacing Between Traces
30
50
100
µm
-
Routing Channel Trace Width
10
30
50
µm
-
3.9 PCB Assembly and Soldering
It is important to follow PCB assembly and soldering standards and guidelines for any CapSense design. Although
CapSense PCB assembly and soldering do not have any specific guidelines, the following specifications and the
application notes give the standard and guidelines respectively.
IPC-A-610, Acceptability of Electronic Assemblies
AN72845 - Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices
AN69061- Design, Manufacturing, and Handling Guidelines for Cypress Wafer Level Chip Scale Packages