Cypress AutoStore STK17T88 Скачать руководство пользователя страница 17

Страница: 17 / 22

STK17T88

Document Number: 001-52040 Rev. *A

Page 17 of 22

RTC Register Map

*A binary value, not a BCD value.

0 - Not implemented, reserved for future use.

Default Settings of nonvolatile Calibration and Interrupt registers from factory

Calibration Register=00h

Interrupt Register=00h

The User should configure to the desired value at startup or during operation and the value is then retained during a power failure.

[ ] designates values shipped from the factory. See

Stopping and Starting the RTC Oscillator

on page 14.

Register

BCD Format Data

Function / Range

0x7FFF

10s Years

Years

Years: 00-99

0x7FFE

10s

Months

Months: 01-12

0x7FFD

10s Day of Month

Day of Month

Day of Month: 01-31

0x7FFC

Day of Week

Day of week: 01-07

0x7FFB

10s Hours

Hours

Hours: 00-23

0x7FFA

10s Minutes

Minutes

Minutes: 00-59

0x7FF9

10s Seconds

Seconds

Seconds: 00-59

0x7FF8

OSCEN

[0]

Cal

Sign

Calibration [00000]

Calibration values*

0x7FF7

WDS

WDW

WDT

Watchdog*

0x7FF6

WIE[0]

AIE[0]

PFE[0]

H/L [1]

P/L [0]

Interrupts*

0x7FF5

10s Alarm Date

Alarm Day

Alarm, Day of Month: 01-31

0x7FF4

10s Alarm Hours

Alarm Hours

Alarm, hours: 00-23

0x7FF3

10 Alarm Minutes

Alarm Minutes

Alarm, minutes: 00-59

0x7FF2

10 Alarm Seconds

Alarm Seconds

Alarm, seconds: 00-59

0x7FF1

10s Centuries

Centuries

Centuries: 00-99

0x7FF0

WDF

OSCF

CAL[0]

W[0]

R[0]

Flags*

[+] Feedback

Содержание AutoStore STK17T88

Страница 1: ...nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell The SRAM provides the fast access and cycle times ease of use and unlimited read and write endurance of a normal SRAM Data transfers automatically to the nonvolatile storage cells when power loss is detected the STORE operation On power up data is automatically restored to the SRAM the RECALL...

Страница 2: ...t Enable The active low G input enables the data output buffers during read cycles De asserting G high caused the DQ pins to tri state X1 Output Crystal Connection drives crystal on startup X2 Input Crystal Connection for 32 768 kHz crystal VRTCcap Power Supply Capacitor supplied backup RTC supply voltage Left unconnected if VRTCbat is used VRTCbat Power Supply Battery supplied backup RTC supply v...

Страница 3: ...s not source or sink high current when interrupt Register bit D3 is below DC Characteristics VCC 2 7V 3 6V Symbol Parameter Commercial Industrial Units Notes Min Max Min Max ICC1 Average VCC Current 65 50 70 55 mA mA tAVAV 25 ns tAVAV 45 ns Dependent on output loading and cycle rate Values obtained without output loads ICC2 Average VCC Current during STORE 3 3 mA All Inputs Don t Care VCC max Aver...

Страница 4: ...OL Output Logic 0 Voltage 0 4 0 4 V IOUT 4 mA TA Operating Temper ature 0 70 40 85 C VCC Operating Voltage 2 7 3 6 2 7 3 6 V 3 0V 20 10 VCAP Storage Capacitance 17 57 17 57 µF Between VCAP pin and VSS 5V rated NVC Nonvolatile STORE operations 200 200 K DATAR Data Retention 20 20 Years At 55 C DC Characteristics continued VCC 2 7V 3 6V Symbol Parameter Commercial Industrial Units Notes Min Max Min ...

Страница 5: ...ttery Pin Voltage 1 8 3 3 1 8 3 3 V Typical 3 0 Volts during normal operation VRTCcap RTC Capacitor Pin Voltage 1 2 2 7 1 2 2 7 V Typical 2 4 Volts during normal operation tOSCS RTC Oscillator time to start 10 10 sec At Minimum Temperature from Power up or Enable 5 5 sec At 25 C from Power up or Enable C 1 C 2 RF Y 1 X1 X2 Recommended Values Y1 32 768 KHz 10M Ohm 0 install cap footprint but leave ...

Страница 6: ... Enable Access Time 25 45 ns 2 tAVAV 3 tELEH 5 tRC Read Cycle Time 25 45 ns 3 tAVQV 4 tAVQV 6 tAA Address Access Time 25 45 ns 4 tGLQV tOE Output Enable to Data Valid 12 20 ns 5 tAXQX 4 tAXQX tOH Output Hold after Address Change 3 3 ns 6 tELQX tLZ Address Change or Chip Enable to Output Active 3 3 ns 7 tEHQZ tHZ Address Change or Chip Disable to Output Inactive 10 15 ns 8 tGLQX tOLZ Output Enable ...

Страница 7: ...Write 20 30 ns 15 tDVWH tDVEH tDW Data Set up to End of Write 10 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns 17 tAVWH tAVEH tAW Address Set up to End of Write 20 30 ns 18 tAVWL tAVEL tAS Address Set up to Start of Write 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns 20 tWLQZ tWZ Write Enable to Output Disable 10 15 ns 21 tWHQX tOW Output Active after End of Write...

Страница 8: ...tile cycle no STORE will take place 11 Industrial Grade Devices require 15 ms Max NO Symbols Parameter STK17T88 Units Notes Standard Alternate Min Max 22 tHRECALL Power up RECALL Duration 40 ms 9 23 tSTORE tHLHZ STORE Cycle Duration 12 5 ms 10 11 24 VSWITCH Low Voltage Trigger Level 2 65 V 25 VCCRISE VCC Rise Time 150 µS NOTE Read and Write cycles will be ignored during STORE RECALL and while VCC ...

Страница 9: ...ernate Min Max Min Max 26 tAVAV tRC STORE RECALL Initiation Cycle Time 25 45 ns 13 27 tAVEL tAS Address Set up Time 0 0 ns 28 tELEH tCW Clock Pulse Width 20 30 ns 29 tEHAX Address Hold Time 1 1 ns 30 tRECALL RECALL Duration 100 100 ms 26 26 27 28 29 23 30 Notes 12 The software sequence is clocked on the falling edge of E controlled READs 13 The six consecutive addresses must be read in the order l...

Страница 10: ...23 31 NO Symbols Parameter STK17T88 Units Notes Standard Min Max 33 tSS Soft Sequence Processing Time 70 µs 15 16 33 33 Notes 14 On a hardware STORE initiation SRAM operation continues to be enabled for time tDELAY to allow read write cycles to complete 15 This is the amount of time that it takes to take action on a soft sequence command Vcc power must remain high to effectively register command 1...

Страница 11: ...8 19 0x0FC0 Nonvolatile Store Output High Z ICC2 L H L 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z Active 17 18 19 Notes 17 The six consecutive addresses must be in the order listed W must be high during all six consecutive cycles to enable a nonvolatile cycl...

Страница 12: ...connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically disconnects the VCAP pin from VCC A STORE operation is initiated with power provided by the VCAP capacitor Figure 5 shows the proper connection of the storage capacitor VCAP for automatic store operation Refer to the DC Charac...

Страница 13: ...s detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The STK17T88 is a high speed memory and so must have a high frequency bypass capacitor of 0 1 µF connected between both VCC pins and VSS ground plane with no plane break to chip VSS Use leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of pow...

Страница 14: ...ct the battery to the VRTCbat pin and leave the VRTCcap pin unconnected A 3V lithium is recommended for this application The battery capacity should be chosen for the total anticipated cumulative down time required over the life of the system The real time clock is designed with a diode internally connected to the VRTCbat pin This prevents the battery from ever being charged by the circuit Stoppin...

Страница 15: ...e software must reload the watchdog timer before it counts down to zero to prevent this interrupt or reset The watchdog timer is a free running down counter that uses the 32Hz clock 31 25 ms derived from the crystal oscillator The watchdog timer function does not operate unless the oscillator is running The watchdog counter is loaded with a starting value from the load register and then counts dow...

Страница 16: ...utput is maintained even when power is lost Pulse Level P L When set to a 1 the INT pin is driven for approximately 200 ms when the interrupt occurs The pulse is reset when the Flags register is read When P L is set to a 0 the INT pin is driven high or low determined by H L until the Flags register is read The Interrupt register is loaded with the default value 00h at the factory The user should c...

Страница 17: ...Years Years Years 00 99 0x7FFE 0 0 0 10s Months Months Months 01 12 0x7FFD 0 0 10s Day of Month Day of Month Day of Month 01 31 0x7FFC 0 0 0 0 0 Day of Week Day of week 01 07 0x7FFB 0 0 10s Hours Hours Hours 00 23 0x7FFA 0 10s Minutes Minutes Minutes 00 59 0x7FF9 0 10s Seconds Seconds Seconds 00 59 0x7FF8 OSCEN 0 0 Cal Sign Calibration 00000 Calibration values 0x7FF7 WDS WDW WDT Watchdog 0x7FF6 WI...

Страница 18: ... D1 D0 0 0 10s Hours Hours Contains the BCD value of hours in 24 hour format Lower nibble contains the lower digit and operates from 0 to 9 upper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 0x7FFA Real Time Clock Minutes D7 D6 D5 D4 D3 D2 D1 D0 0 10s Minutes Minutes Contains the BCD value of minutes Lower nibble contains the lower digit and ...

Страница 19: ...e INT pin is driven to an active level as set by H L until the Flags register is read 0x7FF5 Alarm Day D7 D6 D5 D4 D3 D2 D1 D0 M 0 10s Alarm Date Alarm Date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value M Match Setting this bit to 0 causes the date value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore...

Страница 20: ...register Interrupt register and Flags register Setting the W bit to 0 disables writes to the registers and causes the contents of the real time clock registers to be transferred to the timekeeping counters if the time has changed a new base time is loaded The bit defaults to 0 on power up R Read Time Setting the R bit to 1 captures the current time in holding registers so that clock updates are no...

Страница 21: ...STK17T88 Document Number 001 52040 Rev A Page 21 of 22 Package Diagram Figure 16 48 Pin SSOP 51 85061 51 85061 C Feedback ...

Страница 22: ...modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to ...

Результаты поиска

Содержание AutoStore STK17T88

Отзывы:

Похожие инструкции для AutoStore STK17T88

Бренды по названию

Популярные бренды

Cypress AutoStore STK17T88, Техническое описание

Результаты поиска

Содержание AutoStore STK17T88

Отзывы:

Похожие инструкции для AutoStore STK17T88

Бренды по названию

Популярные бренды