Cypress AN94024, Начало работы

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Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
www.cypress.com
Document No. 001-94024 Rev.*A 6
Output Subsystem
CY27410 consists of two banks of outputs. Each bank
consists of six outputs with OUT11
–OUT14 and OUT21–
OUT24 supporting both differential and single-ended
outputs
and OUT15
–OUT16 and OUT25–OUT26
supporting only single-ended outputs. Each output is fed
from a PLL through a divider and then to a MUX, which
helps in selecting the source for the output, as shown in
Figure 12 and Figure 13 .
Figure 12. Output Bank 1
Figure 13. Output Bank 2
Output Termination
CY27410 supports LVCMOS, LVPECL, CML, LVDS, and
HCSL standards for output. This section describes the
recommended termination circuits for the outputs.
HCSL Output Standard
HCSL interface standard is a differential I/O standard and
is defined in PCIe SIG standard.
Figure 14 shows the
typical interface termination, while Table 3 summarizes the
recommended trace length parameters and termination
resistors.
Figure 14. Typical HSCL Interface Termination
Z=50
W
Z=50
W
RT RT
RS
RS
L1 L2 L3
Table 3. HSCL Interface Parameters
Parameter Value Unit
L1 length 0.5 (max) Inch
L2 length 0.2 (max) Inch
L3 length 10 Inch
RS 33 (3.3 V or 2.5 V supply) Ohm
RS 20 (1.8 V supply) Ohm
RT 49.9 Ohm
LVPECL Output Standard
LVPECL standard signaling level is a differential I/O
standard and is defined in JEDEC JESD8-2 (Emitter
Coupled Logic).
Figure 15 shows the typical termination
scheme for this standard.
Figure 15. LVPECL Output Termination Scheme
Z=50
W
Z=50
W
RT RT
V
TT
=VDD -2 V
In the above scheme, RT= 50
W
Since VDD
– 2 V (1.3 V for 3.3-V operation) may be
difficult to generate, you may use the Y-Termination
instead (see
Figure 16 ).
Figure 16. Y-Termination Scheme
Z=50
W
Z=50
W
RT RT
RTT