Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
Document No. 001-94024 Rev.*A
5
Input Reference System
shows the input reference system of CY27410.
IN1 and XO signal will be multiplexed and fed to internal
reference as IN1B. IN2 can be used for feedback input in
ZDB mode or can be used as another input reference
clock for NZDB mode.
The output from DIV-C of PLL3 is the special-purpose
input that will be used, if you need more than four copies
of the same clocks.
Figure 7. Input Reference System of CY27410
INC
(from PLL3)
IN1B
INI
IN2B
DIV R1
DIV R2
IN1P
IN2P
IN1S
IN2S
XO
IN1N
IN2N
XIN
XOUT
Differential Input Signals
The CY27410 supports various differential I/O standards
like LVPECL, CML, LVDS and HCSL. These I/O standards
have different common mode voltages. The common-
mode voltage (VCM) for various interface standards are
VDD - 1.2 V (LVPECL), VDD - 0.2 V (CML), 1.2 V (LVDS),
and 0.4 V (HCSL).
To maintain multiple differential signals, inputs must be
AC-coupled (100-pF capacitors in series), and termination
resistors should be added outside if needed.
illustrates this design recommendation.
Figure 8. Sample Design Recommendation for Differential
I/O Standards
T
e
rm
in
a
ti
o
n
IN_P
IN_N
ATLAS
PECL,CML,
LVDS,HCSL
Bias
Bias
As described in the previous section, CY27410 accepts
multiple differential signals using AC-coupled inputs. The
input swing amplitude should be more than 300 mV pp for
the signal to meet the VIH/VIL specifications.
LVCMOS Input Signal
shows a simplified LVCMOS input buffer
structure of CY27410. The CMOS input signal is AC-
coupled inside the device. Cypress recommends the
minimum peak-to-peak amplitude to be 300 mV. Both the
inputs are pulled down internally in LVCMOS configuration,
so unused pins can be left floating for CMOS input.
The input circuit of CY27410 uses overvoltage-tolerant
cells. In case an input voltage is applied higher than VDD,
it will not cause any reliability issues. Multiple input voltage
levels can be interfaced to CY27410. Any combination of
different voltages may be used (VDD core=1.8 V, 2.5 V, or
3.3 V, and input voltage level=1.8 V, 2.5 V, or 3.3 V)
Figure 9. Simplified LVCMOS Input Buffer Structure
ATLAS
LVCMOS
Clipped Sine Wave Signal
A typical TCXO output signal is a clipped sine-wave signal.
CY27410 treats this input signal in the same manner as
LVCMOS. The device guarantees only functional
operation when using clipped sine-wave inputs. The
datasheet parameters are not guaranteed for clipped sine-
wave inputs.
Do not use a series capacitor between TCXO and IN1_P if
the CY27410 input mode is configured as LVCMOS
(typically recommended by TCXO vendors). Use a series
capacitor if the input setting is configured as differential.
Figure 10. Connection to the TCXO module
The typical TCXO output signal is shown in figure 11. The
typical peak-to-peak voltage (V
P-P
) is 0.8 V-1.0 V.
Figure 11. Typical TCXO Output Signal
0.8-1.0V
Typ.
