Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
Document No. 001-94024 Rev.*A
3
ZDB Mode
In ZDB mode, the device acts as a zero-propagation-delay
device from input to output as shown in
. In order
to achieve this functionality, CY27410 requires a feedback
clock from one of the outputs for tracking its phase.
Figure 2. ZDB Configuration
Input frequency range (Single Ended): 8 MHz to 250 MHz
Input frequency range (Differential): 8 MHz to 300 MHz
Typical ZDB input/output delay is less than 250 ps.
CY27410 can also provide the Frequency Multiplying/
Dividing ZDB configuration by modifying R1 or R2 divider
appropriately.
When R1 = R2, the output frequency is the same as IN1,
when R1 value is half of R2, the output will be twice of IN1.
CY27410 provides R1 and R2 value of 1, 2, 4, or 8, so you
can configure CY27410 as ZDB with the frequency
multiplying/dividing function.
NZDB Mode
In NZDB mode, the device acts as simple buffering of the
input signal to outputs, also known as fan-out buffer. In the
NZDB mode as shown in
, the PLL is bypassed
making the device act as a fanout buffer.
Input frequency range (Single-Ended): 8 MHz to 250 MHz
Input frequency range (Differential): 8 MHz to 700 MHz
Figure 3. NZDB Configuration
CY27410 can also be configured in combination of
CLKGEN and ZDB, CLKGEN and NZDB, and ZDB and
NZDB modes. This offers unprecedented flexibility to the
customer.
mode can be used in CY27410.
Figure 4: CLKGEN AND NZDB Configuration
Input Subsystem
The device can accept both crystal and reference input.
The crystal input pins are XIN and XOUT, which are
connected to a crystal oscillator block to generate the
required clock to be fed into the VCO. The differential
tuning-capacitor range supported is 8 pF to 12 pF.
The device also support four reference input pins (IN1P,
IN1N, IN2P, and IN2N). These pins are designed to
receive a reference input which can either be single-ended
or differential clock.
IN1 is multiplexed with IN1 (clock signal: single-ended or
differential) or crystal oscillator.
IN2 can be configured as differential or single-ended.
See
for input frequency specifications.
Table 1. Input Frequency Specifications
Input Frequency
Min.
Max.
Crystal
8 MHz
48 MHz
IN1,2-SE
8 MHz
250 MHz
IN1,2-DE
8 MHz
700 MHz
Note
CY27410 incorporates a narrow-bandwidth PLL
(VCO). Therefore, you cannot use the reference clock that
has large distortion/drift; for example, spread-spectrum
clock (typically 0.5 to 1.0% modulation). Switching from
one frequency to another (different) frequency cannot be
used as the reference clock either.
