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Cypress 001-07160, Техническое описание

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18-Mbit DDR II SRAM 2-Word

Burst Architecture

CY7C1318CV18
CY7C1320CV18

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document Number: 001-07160 Rev. *F

 Revised August 24, 2009

Features

■

18-Mbit Density (1M x 18, 512K x 36)

■

267 MHz Clock for high Bandwidth

■

2-word Burst for reducing Address Bus Frequency 

■

Double Data Rate (DDR) Interfaces 

(data transferred at 534 MHz) at 267 MHz 

■

Two Input Clocks (K and K) for precise DDR Timing

❐

SRAM uses rising edges only

■

Two Input Clocks for Output Data (C and C) to minimize Clock 

Skew and Flight Time mismatches

■

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed 

Systems

■

Synchronous internally Self-timed Writes

■

DDR II operates with 1.5 Cycle Read Latency when the DLL is 

enabled

■

Operates similar to a DDR I Device with one Cycle Read 

Latency in DLL Off Mode

■

1.8V Core Power Supply with HSTL Inputs and Outputs

■

Variable drive HSTL Output Buffers

■

Expanded HSTL Output Voltage (1.4V–V

DD

)

■

Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■

Offered in both Pb-free and non Pb-free Packages

■

JTAG 1149.1 compatible Test Access Port

■

Delay Lock Loop (DLL) for accurate Data Placement

Configurations

CY7C1318CV18 – 1M x 18
CY7C1320CV18 – 512K x 36

Functional Description

The CY7C1318CV18, and CY7C1320CV18 are 1.8V

Synchronous Pipelined SRAMs equipped with DDR II archi-

tecture. The DDR II consists of an SRAM core with advanced

synchronous peripheral circuitry and a one-bit burst counter.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of C and C if provided, or on the rising edge of K and K if C/C are

not provided. For CY7C1318CV18 and CY7C1320CV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words (in the case of

CY7C1318CV18) of two 36-bit words (in the case of

CY7C1320CV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description

267 MHz

250 MHz

200 MHz

167 MHz

Unit

Maximum Operating Frequency 

267

250

200

167

MHz

Maximum Operating Current 

x18

805

730

600

510

mA

x36

855

775

635

540

[+] Feedback 

Содержание 001-07160

Страница 1: ...R II archi tecture The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a one bit burst counter Addresses for read and write are latched on alternate rising edges of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the rising edges of C and C if provided or on the rising edge of K and K if C C are not provided F...

Страница 2: ...gic Reg Reg Reg 18 36 18 BWS 1 0 VREF Write Add Decode 18 20 C C 18 LD Control Burst Logic A0 A 19 1 R W DOFF 512K x 18 Array 512K x 18 Array 19 18 DQ 17 0 18 CQ CQ Write Reg Write Reg CLK A 18 0 Gen K K Control Logic Address Register Read Add Decode Read Data Reg R W Output Logic Reg Reg Reg 36 72 36 BWS 3 0 VREF Write Add Decode 36 19 C C 36 LD Control Burst Logic A0 A 18 1 R W DOFF 256K x 36 Ar...

Страница 3: ... VSS VSS NC DQ1 NC N NC NC DQ16 VSS A A A VSS NC NC NC P NC NC DQ17 A A C A A NC NC DQ0 R TDO TCK A A A C A A A TMS TDI CY7C1320CV18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M NC 36M R W BWS2 K BWS1 LD A NC 72M CQ B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 C NC NC DQ28 VSS A A0 A VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ3...

Страница 4: ...d when the appropriate port is deselected R W Input Synchronous Synchronous Read Write Input When LD is LOW this input designates the access type read when R W is HIGH write when R W is LOW for the loaded address R W must meet the setup and hold times around the edge of K C Input Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C...

Страница 5: ...G TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 36M N A Not Connected to the Die Can be tied to any voltage level NC 72M N A Not Connected to the Die Can be tied to any voltage level NC 144M N A Not Connected to the Die Can be tied to any voltage level NC 288M N A Not Connected to the Die Can be tied to any voltage level V...

Страница 6: ... fashion On the following K clock rise the data presented to D 17 0 is latched and stored into the 18 bit write data register provided BWS 1 0 are both asserted active On the subsequent rising edge of the negative input clock K the infor mation presented to D 17 0 is also stored into the write data register provided BWS 1 0 are both asserted active The 36 bits of data are then written into the mem...

Страница 7: ...r the echo clocks is shown in Switching Characteristics on page 20 DLL These chips use a Delay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the DLL is locked after 1024 cycles of stable clock The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it i...

Страница 8: ...During the data portion of a write sequence Only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence Only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H H L H No data is written into the devices during this portion of a write operation H H L H No data is written into the devices during this portion...

Страница 9: ...te D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 18 is written into the device D 17 0 and D 35 27 remains unaltered H H L H L H During the data portion of a writ...

Страница 10: ...dge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 13 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state a...

Страница 11: ...egister Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD ph...

Страница 12: ...llows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR Note 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback ...

Страница 13: ...ge 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are sp...

Страница 14: ...ld after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 14 Figure 2 TAP Timing and Test Conditions tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock Test Mode Select TCK TMS Test Data I...

Страница 15: ...tures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for ...

Страница 16: ...P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43 11C 71 1D 99 2P 16 9N 44 9B 72 2C 100 1P 17 11L 45 10B 73 3E 101 3R 18 11M 46 11A 74 2D 102 4R 19 9L 47 Internal 75 2E 103 4P 20 10L 48 9A 76 1E 104 5P 21 11K 49 8B 77 2F 105 5N 22 10K 50 7C 78 3...

Страница 17: ... 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide1024 cycles stable clock to relock to t...

Страница 18: ...rial Failure Rates Electrical Characteristics DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit VDD Power Supply Voltage 1 7 1 8 1 9 V VDDQ I O Supply Voltage 1 4 1 5 VDD V VOH Output HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Im...

Страница 19: ... affect these parameters Parameter Description Test Conditions 165 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 18 7 C W ΘJC Thermal Resistance Junction to Case 4 5 C W Figure 4 AC Test Loads and Waveforms Electrical Characteristics continued DC Electrical Chara...

Страница 20: ...6 0 7 ns tSC tIVKH Control Setup to K Clock Rise LD R W 0 3 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 35 0 4 0 5 ns tSD tDVKH D X 0 Setup to Clock K and K Rise 0 3 0 35 0 4 0 5 ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0 3 0 5 0 6 0 7 ns tHC tKHIX Control Hold after K Clock Rise LD R W 0 3 0 5 0 6 0 7 ns tHCDDR tKHIX Double...

Страница 21: ...5 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 24 25 0 45 0 45 0 45 0 50 ns DLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 20 0 20 0 20 ns tKC lock tKC lock DLL Lock Time K C 1024 1024 1024 1024 Cycles tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 ns Switching Characteristics continued Over the Operating Range 20 21 Cypress Parameter Consortium Parameter Description 267 MHz ...

Страница 22: ...C A0 D20 D21 D30 D31 Q00 Q11 Q01 Q10 A1 A2 A3 A4 Q41 tCCQO tCQOH tCCQO tCQOH tKL tCYC K K LD R W A DQ C C CQ CQ SA tKH tKHKH tCQD tCQDOH tCQH tCQHCQH Notes 26 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 that is A0 1 27 Outputs are disabled High Z one clock cycle after a NOP 28 In this example if address A4 A3 then data Q40 D30 and Q41...

Страница 23: ... MHz Ordering Code Package Diagram Package Type Operating Range 267 CY7C1318CV18 267BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Commercial CY7C1320CV18 267BZXC 250 CY7C1318CV18 250BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1320CV18 250BZC CY7C1318CV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free C...

Страница 24: ... A B Ø0 08 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A A 15 00 0 10 13 00 0 10 B C 1 00 5 00 0 36 0 06 0 14 1 40 MAX SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD NOTES PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 ISSUE E PACKAGE C...

Страница 25: ... final Updated Logic Block diagram Removed 300 MHz and 278 MHz speed bins Added 267 MHz speed bin Updated IDD ISB specs Changed DLL minimum operating frequency from 80MHz to 120MHz Changed tCYC max spec to 8 4ns Modified footnotes 20 and 28 D 2507747 See ECN VKN PYRS Changed Ambient Temperature with Power Applied from 10 C to 85 C to 55 C to 125 C in the Maximum Ratings on page 20 Updated power up...

Страница 26: ...fy create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified...

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